View CY8C5387PVI-031_5041435.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PRELIMINARY PSoC(R) 5: CY8C53 Family Datasheet Programmable System-on-Chip (PSoC(R))
General Description
With its unique array of configurable blocks, PSoC(R) 5 is a true system level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C53 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals. The CY8C53 family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The CY8C53 family is also a high-performance configurable digital system with some part numbers including interfaces such as USB, multi-master I2C, and controller area network (CAN). In addition to communication interfaces, the CY8C53 family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit ARM(R) CortexTM-M3 microprocessor core. Designers can easily create system-level designs using a rich library of prebuilt components and boolean primitives using PSoC(R) CreatorTM, a hierarchical schematic design entry tool. The CY8C53 family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.
Features
32-bit ARM Cortex-M3 CPU core

DC to 80 MHz operation Flash program memory, up to 256 KB, 100,000 write cycles, 20-year retention, multiple security features Up to 64 KB SRAM memory 2-KB electrically erasable programmable read-only memory (EEPROM) memory, 1 million cycles, and 20 years retention 24-channel direct memory access (DMA) with multilayer AMBA high-performance bus (AHB) bus access * Programmable chained descriptors and priorities * High bandwidth 32-bit transfer support Low voltage, ultra low power Wide operating voltage range: 0.5 V to 5.5 V High efficiency boost regulator from 0.5 V input to 1.8 V to 5.0 V output 2 mA at 6 MHz Low power modes including: * 2-A sleep mode with real time clock (RTC) and low-voltage detect (LVD) interrupt * 300-nA hibernate mode with RAM retention Versatile I/O system [1] 28 to 72 I/Os (62 GPIOs, 8 SIOs, 2 USBIOs ) Any GPIO to any digital or analog peripheral routability LCD direct drive from any GPIO, up to 46x16 segments (R) [2] CapSense support from any GPIO 1.2 V to 5.5 V I/O interface voltages, up to 4 domains Maskable, independent IRQ on any pin or port Schmitt-trigger transistor-transistor logic (TTL) inputs All GPIOs configurable as open drain high/low, pull-up/pull-down, High-Z, or strong output Configurable GPIO pin state at power-on reset (POR) 25 mA sink on SIO Digital peripherals 20 to 24 programmable logic device (PLD) based universal digital blocks (UDBs) [1] Full CAN 2.0b 16 RX, 8 TX buffers [1] Full-Speed (FS) USB 2.0 12 Mbps using internal oscillator Up to four 16-bit configurable timer, counter, and PWM blocks Library of standard peripherals * 8-, 16-, 24-, and 32-bit timers, counters, and PWMs * SPI, UART, and I2C * Many others available in catalog
Library of advanced peripherals * Cyclic redundancy check (CRC) * Pseudo random sequence (PRS) generator * Local interconnect network (LIN) bus 2.0 * Quadrature decoder Analog peripherals (1.71 V VDDA 5.5 V) 1.024 V 0.1% internal voltage reference across -40 C to +85 C (14 ppm/C) Successive approximation register (SAR) analog-to-digital converter (ADC), 12-bit at 1 Msps Two 8-bit 8 Msps current digital-to-analog converters (DAC) (IDACs) or 1 Msps voltage DACs (VDACs) Four comparators with 95-ns response time Two uncommitted opamps with 25-mA drive capability Two configurable multifunction analog blocks. Example configurations are programmable gain amplifier (PGA), transimpedance amplifier (TIA), mixer, and sample and hold CapSense support
Programming, debug, and trace
JTAG (4-wire), serial wire debug (SWD) (2-wire), single-wire viewer (SWV), and TRACEPORT interfaces Cortex-M3 flash patch and breakpoint (FPB) block Cortex-M3 Embedded Trace MacrocellTM (ETMTM) generates an instruction trace stream. Cortex-M3 data watchpoint and trace (DWT) generates data trace information Cortex-M3 instrumentation trace macrocell (ITM) can be used for printf-style debugging DWT, ETM, and ITM blocks communicate with off-chip debug and trace systems via the SWV or TRACEPORT 2 Bootloader programming supportable through I C, SPI, UART, USB, and other interfaces Precision, programmable clocking 3- to 74-MHz internal oscillator over full temperature and voltage range 4- to 33-MHz crystal oscillator for crystal PPM accuracy Internal PLL clock generation up to 80 MHz 32.768-kHz watch crystal oscillator Low power internal oscillator at 1, 33, and 100 kHz Temperature and packaging -40C to +85C degrees industrial temperature 48-pin SSOP, 68-pin QFN, and 100-pin TQFP package options
Notes 1. This feature on select devices only. See Ordering Information on page 91 for details. 2. GPIOs with opamp outputs are not recommended for use with CapSense
Cypress Semiconductor Corporation Document Number: 001-55035 Rev. *G
*
198 Champion Court
*
San Jose, CA 95134-1709
* 408-943-2600 Revised September 2, 2010
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Contents
1. Architectural Overview ................................................ 3 2. Pinouts .......................................................................... 5 3. Pin Descriptions ........................................................... 9 4. CPU .............................................................................. 10 4.1 ARM Cortex-M3 CPU .......................................... 10 4.2 Cache Controller ................................................. 12 4.3 DMA and PHUB .................................................. 12 4.4 Interrupt Controller .............................................. 14 5. Memory ........................................................................ 16 5.1 Static RAM .......................................................... 16 5.2 Flash Program Memory ....................................... 16 5.3 Flash Security ...................................................... 16 5.4 EEPROM ............................................................. 16 5.5 External Memory Interface .................................. 16 5.6 Memory Map ....................................................... 18 6. System Integration ..................................................... 19 6.1 Clocking System .................................................. 19 6.2 Power System ..................................................... 23 6.3 Reset ................................................................... 26 6.4 I/O System and Routing ...................................... 28 7. Digital Subsystem ...................................................... 34 7.1 Example Peripherals ........................................... 34 7.2 Universal Digital Block ......................................... 38 7.3 UDB Array Description ........................................ 41 7.4 DSI Routing Interface Description ....................... 42 7.5 CAN ..................................................................... 43 7.6 USB ..................................................................... 45 7.7 Timers, Counters, and PWMs ............................. 46 7.8 I2C ....................................................................... 46 8. Analog Subsystem ..................................................... 47 8.1 Analog Routing .................................................... 48 8.2 Successive Approximation ADC .......................... 50 8.3 Comparators ........................................................ 50 8.4 Opamps ............................................................... 52 8.5 Programmable SC/CT Blocks ............................. 52 8.6 LCD Direct Drive ................................................. 53 8.7 CapSense ............................................................ 54 8.8 Temp Sensor ....................................................... 54 8.9 DAC ..................................................................... 54 8.10 Up/Down Mixer .................................................. 55 8.11 Sample and Hold ............................................... 56 9. Programming, Debug Interfaces, Resources ........... 56 9.1 JTAG Interface .................................................... 57 9.2 SWD Interface ..................................................... 57 9.3 Debug Features ................................................... 57 9.4 Trace Features .................................................... 57 9.5 SWV and TRACEPORT Interfaces ..................... 57 9.6 Programming Features ........................................ 57 9.7 Device Security ................................................... 57 10. Development Support .............................................. 58 10.1 Documentation .................................................. 58 10.2 Online ................................................................ 58 10.3 Tools .................................................................. 58 11. Electrical Specifications .......................................... 59 11.1 Absolute Maximum Ratings ............................... 59 11.2 Device Level Specifications ............................... 60 11.3 Power Regulators .............................................. 62 11.4 Inputs and Outputs ............................................ 63 11.5 Analog Peripherals ............................................ 69 11.6 Digital Peripherals ............................................. 78 11.7 Memory ............................................................. 81 11.8 PSoC System Resources .................................. 86 11.9 Clocking ............................................................. 88 12. Ordering Information ................................................ 91 12.1 Part Numbering Conventions ............................ 93 13. Packaging .................................................................. 94 14. Acronyms .................................................................. 96 15. Reference Documents .............................................. 97 16. Document Conventions ........................................... 98 16.1 Units of Measure ............................................... 98 17. Revision History ....................................................... 99 18. Sales, Solutions, and Legal Information .............. 102
Document Number: 001-55035 Rev. *G
Page 2 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
1. Architectural Overview
Introducing the CY8C53 family of ultra low-power, flash Programmable System-on-Chip (PSoC(R)) devices, part of a scalable 8-bit PSoC 3 and 32-bit PSoC 5 platform. The CY8C53 family provides configurable blocks of analog, digital, and interconnect circuitry around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables a high level of integration in a wide variety of consumer, industrial, and medical applications. Figure 1-1. Simplified Block Diagram
Analog Interconnect Digital Interconnect
GPIOs
Usage Example for UDB
Sequencer
4 to 33 MHz ( Optional )
System Wide Resources
Xtal Osc
Digital System
Universal Digital Block Array (24 x UDB)
8- Bit Timer UDB Quadrature Decoder UDB 16- Bit PWM UDB 16- Bit PRS UDB UDB UDB
CAN 2.0
I2C
Master / Slave
SIO
22
UDB UDB
Clock Tree
UDB I 2C Slave UDB
UDB 8- Bit SPI
UDB 12- Bit SPI
UDB 8- Bit Timer Logic UDB
GPIOs
UDB
UDB
UDB
UDB
IMO
4x Timer Counter PWM
FS USB 2.0
USB PHY
32.768 KHz ( Optional )
Logic UDB UART UDB UDB 12- Bit PWM UDB UDB UDB
RTC Timer
System Bus
WDT and Wake GPIOs
Memory System
EEPROM SRAM
CPU System
8051 or Cortex M3 CPU Interrupt Controller
Program & Debug
Program Debug & Trace
EMIF ILO Clocking System
Power Management System
FLASH
Cache Controller
PHUB DMA
Boundary Scan
Analog System
LCD Direct Drive
SIOs
POR and LVD Sleep Power 1.71 to 5.5 V 1.8 V LDO SMP 2 x SC/ CT Blocks (TIA, PGA, Mixer etc ) Temperature Sensor CapSense
ADC
SAR ADC
+ 2x Opamp -
3 per Opamp
2 x DAC
4x CMP
-
0. 5 to 5.5V ( Optional )
Document Number: 001-55035 Rev. *G
GPIOs
+
GPIOs
GPIOs
GPIOs
Page 3 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Figure 1-1 illustrates the major components of the CY8C53 family. They are:
ARM Cortex-M3 CPU subsystem Nonvolatile subsystem Programming, debug, and test subsystem Inputs and outputs Clocking Power Digital subsystem Analog subsystem
All GPIO pins can route analog signals into and out of the device using the internal analog bus. This allows the device to interface up to 62 discrete analog signals. The CY8C53 family also offers a SAR ADC. Featuring 12-bit conversions at up to 1 M samples per second, it also offers low nonlinearity and offset errors and SNR better than 70 dB. It is well suited for a variety of higher speed analog applications. Two high speed voltage or current DACs support 8-bit output signals at an update rate of up to 8 Msps. They can be routed out of any GPIO pin. You can create higher resolution voltage DAC outputs using the UDB array. This can be used to create a pulse width modulated (PWM) DAC of up to 10 bits, at up to 48 kHz. The digital DACs in each UDB support PWM, PRS, or delta-sigma algorithms with programmable widths. In addition to the ADC and DACs, the analog subsystem provides multiple:
Comparators Uncommitted opamps Configurable switched capacitor/continuous time (SC/CT)
PSoC's digital subsystem provides half of its unique configurability. It connects a digital signal from any peripheral to any pin through the digital system interconnect (DSI). It also provides functional flexibility through an array of small, fast, low-power UDBs. PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM, AND, OR, and so on) that are mapped to the UDB array. The designer can also easily create a digital circuit using boolean primitives by means of graphical design entry. Each UDB contains programmable array logic (PAL)/programmable logic device (PLD) functionality, together with a small state machine engine to support a wide variety of peripherals. In addition to the flexibility of the UDB array, PSoC also provides configurable digital blocks targeted at specific functions. For the CY8C53 family these blocks can include four 16-bit timer, counter, and PWM blocks; I2C slave, master, and multimaster; Full-Speed USB; and Full CAN 2.0b. For more details on the peripherals see the "Example Peripherals" section on page 34 of this datasheet. For information on UDBs, DSI, and other digital blocks, see the "Digital Subsystem" section on page 34 of this datasheet. PSoC's analog subsystem is the second half of its unique configurability. All analog performance is based on a highly accurate absolute voltage reference with less than 0.1% error over temperature and voltage. The configurable analog subsystem includes:
Analog muxes Comparators Analog mixers Voltage references Analog-to-Digital Converters (ADC) Digital-to-Analog Converters (DACs)
blocks. These support: Transimpedance amplifiers Programmable gain amplifiers Mixers Other similar analog components See the "Analog Subsystem" section on page 47 of this datasheet for more details.
PSoC's CPU subsystem is built around a 32-bit three-stage pipelined ARM Cortex-M3 processor running at up to 80 MHz. The Cortex-M3 includes a tightly integrated nested vectored interrupt controller (NVIC) and various debug and trace modules. The overall CPU subsystem includes a DMA controller, flash cache, and RAM. The NVIC provides low latency, nested interrupts, and tail-chaining of interrupts and other features to increase the efficiency of interrupt handling. The DMA controller enables peripherals to exchange data without CPU involvement. This allows the CPU to run slower (saving power) or use those CPU cycles to improve the performance of firmware algorithms. The flash cache also reduces system power consumption by allowing less frequent flash access. PSoC's nonvolatile subsystem consists of flash, byte-writeable EEPROM, and nonvolatile configuration options. It provides up to 256 KB of on-chip flash. The CPU can reprogram individual blocks of flash, enabling boot loaders. The designer can enable an error correcting code (ECC) for high reliability applications. A powerful and flexible protection model secures the user's sensitive information, allowing selective memory block locking for read and write protection. Two KB of byte-writable EEPROM is available on-chip to store application data. Additionally, selected configuration options such as boot speed and pin drive mode are stored in nonvolatile memory. This allows settings to activate immediately after POR.
Document Number: 001-55035 Rev. *G
Page 4 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
The three types of PSoC I/O are extremely flexible. All I/Os have many drive modes that are set at POR. PSoC also provides up to four I/O voltage domains through the VDDIO pins. Every GPIO has analog I/O, LCD drive, flexible interrupt generation, slew rate control, and digital I/O capability. The SIOs on PSoC allow VOH to be set independently of VDDIO when used as outputs. When SIOs are in input mode they are high impedance. This is true even when the device is not powered or when the pin voltage goes above the supply voltage. This makes the SIO ideally suited for use on an I2C bus where the PSoC may not be powered when other devices on the bus are. The SIO pins also have high current sink capability for applications such as LED drives. The programmable input threshold feature of the SIO can be used to make the SIO function as a general purpose analog comparator. For devices with Full-Speed USB the USB physical interface is also provided (USBIO). When not using USB these pins may also be used for limited digital functionality and device programming. All the features of the PSoC I/Os are covered in detail in the "I/O System and Routing" section on page 28 of this datasheet. The PSoC device incorporates flexible internal clock generators, designed for high stability and factory trimmed for high accuracy. The internal main oscillator (IMO) is the master clock base for the system, and has 1% accuracy at 3 MHz. The IMO can be configured to run from 3 MHz up to 74 MHz. Multiple clock derivatives can be generated from the main clock frequency to meet application needs. The device provides a PLL to generate system clock frequencies up to 80 MHz from the IMO, external crystal, or external reference clock. It also contains a separate, very low-power internal low speed oscillator (ILO) for the sleep and watchdog timers. A 32.768-kHz external watch crystal is also supported for use in real time clock (RTC) applications. The clocks, together with programmable clock dividers, provide the flexibility to integrate most timing requirements. The CY8C53 family supports a wide supply operating range from 1.71 to 5.5 V. This allows operation from regulated supplies such as 1.8 5%, 2.5 V 10%, 3.3 V 10%, or 5.0 V 10%, or directly from a wide range of battery types. In addition, it provides an integrated high efficiency synchronous boost converter that can power the device from supply voltages as low as 0.5 V. This enables the device to be powered directly from a single battery or solar cell. In addition, the designer can use the boost converter to generate other voltages required by the device, such as a 3.3 V supply for LCD glass drive. The boost's output is available
on the VBOOST pin, allowing other devices in the application to be powered from the PSoC. PSoC supports a wide range of low-power modes. These include a 300-nA hibernate mode with RAM retention and a 2-A sleep mode with RTC. In the second mode the optional 32.768-kHz watch crystal runs continuously and maintains an accurate RTC. Power to all major functional blocks, including the programmable digital and analog peripherals, can be controlled independently by firmware. This allows low-power background processing when some peripherals are not in use. This, in turn, provides a total device current of only 2 mA when the CPU is running at 6 MHz. The details of the PSoC power modes are covered in the "Power System" section on page 23 of this datasheet. PSoC uses JTAG (4-wire) or SWD (2-wire) interfaces for programming, debug, and test. Using these standard interfaces enables the designer to debug or program the PSoC with a variety of hardware solutions from Cypress or third party vendors. The Cortex-M3 debug and trace modules include FPB, DWT, ETM, and ITM. These modules have many features to help solve difficult debug and trace problems. Details of the programming, test, and debugging interfaces are discussed in the "Programming, Debug Interfaces, Resources" section on page 56 of this datasheet.
2. Pinouts
The VDDIO pin that supplies a particular set of pins is indicated by the black lines drawn on the pinout diagrams in Figure 2-2 and Figure 2-3. Using the VDDIO pins, a single PSoC can support multiple interface voltage levels, eliminating the need for off-chip level shifters. Each VDDIO may sink up to 100 mA total to its associated I/O pins and opamps. On the 68-pin and 100-pin devices each set of VDDIO associated pins may sink up to 100 mA. The 48 pin device may sink up to 100 mA total for all Vddio0 plus Vddio2 associated I/O pins and 100 mA total for all Vddio1 plus Vddio3 associated I/O pins.
Document Number: 001-55035 Rev. *G
Page 5 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
[3]
Figure 2-1. 48-pin SSOP Part Pinout
(SIO) P12[2] (SIO) P12[3] (OpAmp2out, GPIO) P0[0] (OpAmp0out, GPIO) P0[1] (OpAmp0+, GPIO) P0[2] (OpAmp0-/Extref0, GPIO) P0[3] Vddio0 (OpAmp2+, GPIO) P0[4] (OpAmp2-, GPIO) P0[5] (IDAC0, GPIO) P0[6] (IDAC2, GPIO) P0[7] Vccd Vssd Vddd (TRACECLK, GPIO) P2[3] (TRACEDATA[0], GPIO) P2[4] Vddio2 (TRACEDATA[1], GPIO) P2[5] (TRACEDATA[2], GPIO) P2[6] (TRACEDATA[3], GPIO) P2[7] Vssb Ind Vboost Vbat 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
Lines show Vddio to I/O supply association
SSOP
Vdda Vssa Vcca P15[3] (GPIO, kHz XTAL: Xi) P15[2] (GPIO, kHz XTAL: Xo) P12[1] (SIO, I2C1: SDA) P12[0] (SIO, I2C1: SCL) Vddio3 P15[1] (GPIO, MHz XTAL: Xi) P15[0] (GPIO, MHz XTAL: Xo) Vccd Vssd Vddd [3] P15[7] (USBIO, D-, SWDCK) [3] P15[6] (USBIO, D+, SWDIO) P1[7] (GPIO) P1[6] (GPIO) Vddio1 P1[5] (GPIO, nTRST) P1[4] (GPIO, TDI) P1[3] (GPIO, TDO, SWV) P1[2] (GPIO, configurable XRES) P1[1] (GPIO, TCK, SWDCK) P1[0] (GPIO, TMS, SWDIO)
Figure 2-2. 68-pin QFN Part Pinout[4]
P2[5] (GPIO, TRACEDATA[1]) Vddio2 P2[4] (GPIO, TRACEDATA[0]) P2[3] (GPIO, TRACECLK) P0[5] (GPIO, OpAmp2-) P0[4] (GPIO, OpAmp2+) Vddio0 53 52
68 67
66 65
64 63 62 61 60 59
58 57 56
(TRACEDATA[2], GPIO) P2[6] (TRACEDATA[3], GPIO) P2[7] (I2C0: SCL, SIO) P12[4] (I2C0: SDA, SIO) P12[5] Vssb Ind Vboost Vbat Vssd XRES (TMS, SWDIO, GPIO) P1[0] (TCK, SWDCK, GPIO) P1[1] (configurable XRES, GPIO) P1[2] (TDO, SWV, GPIO) P1[3] (TDI, GPIO) P1[4] (nTRST, GPIO) P1[5] Vddio1
55 54
P0[7] (GPIO, IDAC2) P0[6] (GPIO, IDAC0)
P15[5] (GPOI) P15[4] (GPIO) Vddd Vssd Vccd
P2[2] (GPIO) P2[1] (GPIO) P2[0] (GPIO)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
51 50 Lines show Vddio to IO supply association 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35
QFN
(Top View)
P0[3] (GPIO, OpAmp0-/Extref0) P0[2] (GPIO, OpAmp0+) P0[1] (GPIO, OpAmp0out) P0[0] (GPIO, OpAmp2out) P12[3] (SIO) P12[2] (SIO) Vssd Vdda Vssa Vcca P15[3] (GPIO, kHz XTAL: Xi) P15[2] (GPIO, kHz XTAL: Xo) P12[1] (SIO, I2C1: SDA) P12[0] (SIO, 12C1: SCL) P3[7] (GPIO) P3[6] (GPIO) Vddio3
18 19
20 21 22
23
24 25 26 27 Vddd Vssd Vccd (MHz XTAL: Xo, GPIO) P15[0]
(MHz XTAL: Xi, GPIO) P15[1] (GPIO) P3[0] (GPIO) P3[1] (Extref1, GPIO) P3[2]
(GPIO) P3[3] (GPIO) P3[4]
(GPIO) P1[6]
Notes 3. Pins are No Connect (NC) on devices without USB. NC means that the pin has no electrical connection. The pin can be left floating or tied to a supply voltage or ground. 4. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal. Document Number: 001-55035 Rev. *G Page 6 of 102
(GPIO) P1[7] (SIO) P12[6] (SIO) P12[7] [3](USBIO, D+, SWDIO) P15[6] [3] (USBIO, D-, SWDCK) P15[7]
(GPIO) P3[5]
28 29 30 31 32 33 34
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Figure 2-3. 100-pin TQFP Part Pinout
P2[4] ( GPIO, TRA CE DA TA[0]) P2[3] ( GPIO, TRA CE CL K]) P2[2] ( GPIO) P0[6] ( GPIO, IDA C0) P0[5] ( GPIO, OpA mp 2-) P0[4] ( GPIO, OpA mp 2+) 77 76 75 74 Lines show Vddio to I/O supply association 73 72 71 70 69 68 67 66 65 Vddio0 P0[3] (GPIO , OpAmp Extref0) 0-/ P0[2] (GPIO , OpAmp +) 0 P0[1] (GPIO , OpAmp out) 0 P0[0] (GPIO , OpAmp out) 2 P4[1] (GPIO) P4[0] (GPIO) P12[3] (SIO) P12[2] (SIO) Vssd Vdda Vssa Vcca NC NC NC NC NC NC P15[3] ( GPIO, kHz XTAL Xi) : P15[2] ( GPIO, kHz XTAL Xo) : P12[1] (SIO , I2C1 : SDA) P12[0] (SIO , I2C1 : SCL) P3[7] (GPIO) P3[6] (GPIO) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ( GPIO) P 3[5] Vd di o3
100 99
98 97 96
95 94 93 92 91
90 89 88
87 86
85 84 83
( TRACEDATA , GPIO) P2[5] [1] ( TRACEDATA , GPIO) P2[6] [2] ( TRACEDATA , GPIO) P2[7] [3] (I2C0 : SCL, SIO ) P 12[4] (I2C0 : SDA , SIO ) P 12[5] ( GPIO) P6[4] ( GPIO) P6[5] ( GPIO) P6[6] ( GPIO) P6[7] Vssb Ind Vboost Vbat Vssd XRES ( GPIO) P5[0] ( GPIO) P5[1] ( GPIO) P5[2] ( GPIO) P5[3] ( TMS, SWDIO, GPIO) P1[0] ( TCK, SWDCK, GPIO) P1[1] ( configurable XRES GPIO) P1[2] , ( TDO, SWV , GPIO) P1[3] ( TDI, GPIO) P1[4] ( nTRST, GPIO) P1[5]
1 2 3 4
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
TQFP
26 27 28 29 30 31
32 33 34 35
36 37 38 39 40 41 42
43 44 45 46
Vd di o1
V ddd Vssd Vccd
NC NC
(MHz XTAL: Xo, GPIO) P1 5[0] ( MHz XTAL: Xi, GPIO) P1 5[1]
Note 5. Pins are No Connect (NC) on devices without USB. NC means that the pin has no electrical connection. The pin can be left floating or tied to a supply voltage or ground.
Document Number: 001-55035 Rev. *G
( GPIO) P 5[5] ( GPIO) P 5[6] ( GPIO) P 5[7] [5] (USBIO, D+, SWDIO) P1 5[6] [5] ( US BIO, D-, SWDCK) P1 5[7]
( GPIO) P 3[0] ( GPIO) P 3[1] ( Extref1, GPIO) P 3[2] ( GPIO) P 3[3] ( GPIO) P 3[4]
( GPIO) P 1[6] ( GPIO) P 1[7] (SIO) P1 2[6] (SIO) P1 2[7] ( GPIO) P 5[4]
47 48 49 50
24 25
82 81 80 79 78
P4[5] ( GPIO) P4[4] ( GPIO) P4[3] ( GPIO) P4[2] ( GPIO) P0[7] ( GPIO, IDA C2)
P2[1] ( GPIO) P2[0] ( GPIO) P15[5] ( GPIO)
P15[4] ( GPIO) P6[3] ( GPIO) P6[2] ( GPIO) P6[1] ( GPIO) P6[0] ( GPIO)
Vccd P4[7] ( GPIO) P4[6] ( GPIO)
Vddio2
Vdd d Vssd
Page 7 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
on page 23. The trace between the two VCCD pins should be as short as possible.
Figure 2-4 and Figure 2-5 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal analog performance on a 2-layer board.
The two pins labeled VDDD must be connected together. The two pins labeled VCCD must be connected together, with
The two pins labeled VSSD must be connected together.
capacitance added, as shown in Figure 2-4 and Power System Figure 2-4. Example Schematic for 100-pin TQFP Part with Power Connections
Vddd Vddd
Vddd
C1 1 uF
C2 0.1 uF Vccd
C6 0.1 uF Vssd
Vddd 100 99 98 97 96 95 94 93 92 91 90 89 Vddd 88 Vssd 87 86 85 84 83 82 81 80 79 78 77 76 Vssd Vssd
U2 CY8C55xx
Vddio2 P2[4] P2[3] P2[2] P2[1] P2[0] P15[5] P15[4] P6[3] P6[2] P6[1] P6[0] Vddd Vssd Vccd P4[7] P4[6] P4[5] P4[4] P4[3] P4[2] IDAC2, P0[7] IDAC0, P0[6] OA2-, P0[5] OA2+, P0[4]
Vddd 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 C8 0.1 uF Vssd Vssd Vssd Vdda Vssa Vcca C9 1 uF
Vdda
Vssd
Vssd
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 P32 47 48 49 50
Vddd
Vddio1 P1[6] P1[7] P12[6], SIO P12[7], SIO P5[4] P5[5] P5[6] P5[7] USB D+, P15[6] USB D-, P15[7] Vddd Vssd Vccd NC NC P15[0], MHzXout P15[1], MHzXin P3[0], IDAC1 P3[1], IDAC3 P3[2], OA3-, REF1 P3[3], OA3+ P3[4], OA1P3[5], OA1+ Vddio3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
P2[5] P2[6] P2[7] P12[4], SIO P12[5], SIO P6[4] P6[5] P6[6] P6[7] Vssb Ind Vboost Vbat Vssd XRES P5[0] P5[1] P5[2] P5[3] P1[0], SWIO, TMS P1[1], SWDIO, TCK P1[2] P1[3], SWV, TDO P1[4], TDI P1[5], nTRST
Vddio0 OA0-, REF0, P0[3] OA0+, P0[2] OA0out, P0[1] OA2out, P0[0] P4[1] P4[0] SIO, P12[3] SIO, P12[2] Vssd Vdda Vssa Vcca NC NC NC NC NC NC kHzXin, P15[3] kHzXout, P15[2] SIO, P12[1] SIO, P12[0] OA3out, P3[7] OA1out, P3[6]
C17 1 uF
Vssa Vdda
C10 0.1 uF
Vssa
Vddd C11 0.1 uF C14 0.1 uF Vssd
Vssd
Vddd
Vccd
C12 0.1 uF Vssd C16 0.1 uF
C13 10 uF, 6.3 V Vssa
C15 1 uF
Vssa
Vssd
Note The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended, as shown in Figure 2-5.
Document Number: 001-55035 Rev. *G
Page 8 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Figure 2-5. Example PCB Layout for 100-Pin TQFP Part for Optimal Analog Performance
Vssa Vddd Vssd Vdda
Vssd Plane
Vssa Plane
3. Pin Descriptions
IDAC0, IDAC2. Low resistance output pin for high current DACs (IDAC). OpAmp0out, OpAmp2out. High current output of uncommitted opamp[6]. Extref0, Extref1. External reference input to the analog system. OpAmp0-, OpAmp2-. Inverting input to uncommitted opamp. OpAmp0+, OpAmp2+. Noninverting opamp. input to uncommitted
voltage, analog comparator, high sink current, and high impedance state when the device is unpowered. SWDCK. Serial Wire Debug Clock programming and debug port connection. SWDIO. Serial Wire Debug Input and Output programming and debug port connection. TCK. JTAG Test Clock programming and debug port connection. TDI. JTAG Test Data In programming and debug port connection. TDO. JTAG Test Data Out programming and debug port connection. TMS. JTAG Test Mode Select programming and debug port connection. TRACECLK. Cortex-M3 TRACEDATA pins. TRACEPORT connection, clocks
GPIO. General purpose I/O pin provides interfaces to the CPU, digital peripherals, analog peripherals, interrupts, LCD segment drive, and CapSense[6]. I2C0: SCL, I2C1: SCL. I2C SCL line providing wake from sleep on an address match. Any I/O pin can be used for I2C SCL if wake from sleep is not required. I2C0: SDA, I2C1: SDA. I2C SDA line providing wake from sleep on an address match. Any I/O pin can be used for I2C SDA if wake from sleep is not required. Ind. Inductor connection to boost pump. kHz XTAL: Xo, kHz XTAL: Xi. 32.768 kHz crystal oscillator pin. MHz XTAL: Xo, MHz XTAL: Xi. 4 to 33 MHz crystal oscillator pin. nTRST. Optional JTAG Test Reset programming and debug port connection to reset the JTAG connection. SIO. Special I/O provides interfaces to the CPU, digital peripherals and interrupts with a programmable high threshold
TRACEDATA[3:0]. Cortex-M3 output data. SWV. Single Wire Viewer output.
TRACEPORT
connections,
USBIO, D+. Provides D+ connection directly to a USB 2.0 bus. May be used as a digital I/O pin; it is powered from VDDD instead of from a VDDIO. Pins are No Connect (NC) on devices without USB.[3] USBIO, D-. Provides D- connection directly to a USB 2.0 bus. May be used as a digital I/O pin; it is powered from VDDD instead of from a VDDIO. Pins are No Connect (NC) on devices without USB.[3] VBOOST. Power sense connection to boost pump. VBAT. Battery supply to boost pump.
Note 6. GPIOs with opamp outputs are not recommended for use with CapSense Document Number: 001-55035 Rev. *G Page 9 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
VCCA. Output of analog core regulator and input to analog core. Requires a 1 F capacitor to VSSA. Regulator output not for external use. VCCD. Output of digital core regulator and input to digital core. The two VCCD pins must be shorted together, with the trace between them as short as possible, and a 1 F capacitor to VSSD; see Power System on page 23. Regulator output not for external use. VDDA. Supply for all analog peripherals and analog core regulator. VDDA must be the highest voltage present on the device. All other supply pins must be less than or equal to VDDA. VDDD. Supply for all digital peripherals and digital core regulator. VDDD must be less than or equal to VDDA. VSSA. Ground for all analog peripherals. VSSB. Ground connection for boost pump.
VSSD. Ground for all digital logic and I/O pins. VDDIO0, VDDIO1, VDDIO2, VDDIO3. Supply for I/O pins. Each VDDIO must be tied to a valid operating voltage (1.71 V to 5.5 V), and must be less than or equal to VDDA. If the I/O pins associated with Vddio0, Vddio2 or Vddio3 are not used then that VDDIO should be tied to ground (VSSD or VSSA). XRES (and configurable XRES). External reset pin. Active low with internal pullup. In 48-pin SSOP parts, P1[2] is configured as XRES. In all other parts the pin is configured as a GPIO.
4. CPU
4.1 ARM Cortex-M3 CPU
The CY8C53 family of devices has an ARM Cortex-M3 CPU core. The Cortex-M3 is a low power 32-bit three-stage pipelined Harvard architecture CPU that delivers 1.25 DMIPS/MHz. It is intended for deeply embedded applications that require fast interrupt handling features.
Figure 4-1. ARM Cortex-M3 Block Diagram
Interrupt Inputs
Nested Vectored Interrupt Controller (NVIC)
I- Bus D-Bus
Cortex M3 CPU Core
Data Watchpoint and Trace (DWT)
Embedded Trace Module (ETM)
S-Bus
Instrumentation Trace Module (ITM) Trace Port 5 for TRACEPORT or Interface Unit 1 for SWV mode (TPIU)
Trace Pins:
JTAG/SWD
Debug Block (Serial and JTAG)
C-Bus AHB AHB
Flash Patch and Breakpoint (FPB)
Cortex M3 Wrapper
32 KB SRAM
Bus Matrix
Bus Matrix
Cache
256 KB ECC Flash
AHB
32 KB SRAM
Bus Matrix
AHB Bridge & Bus Matrix
PHUB
DMA
AHB Spokes GPIO & EMIF Prog. Digital Prog. Analog Special Functions
Peripherals
Document Number: 001-55035 Rev. *G
Page 10 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
The Cortex-M3 CPU subsystem includes these features:
ARM Cortex-M3 CPU Programmable NVIC, tightly integrated with the CPU core Full-featured debug and trace modules, tightly integrated with
At the user level, access to certain instructions, special registers, configuration registers, and debugging components is blocked. Attempts to access them cause a fault exception. At the privileged level, access to all instructions and registers is allowed. The processor runs in the handler mode (always at the privileged level) when handling an exception, and in the thread mode when not. 4.1.3 CPU Registers The Cortex-M3 CPU registers are listed in Table 4-2. Registers R0-R15 are all 32 bits wide. Table 4-2. Cortex M3 CPU Registers Register R0-R12 Description General purpose registers R0-R12 have no special architecturally defined uses. Most instructions that specify a general purpose register specify R0-R12.
Low Registers: Registers R0-R7 are acces-
the CPU core of SRAM
Up to 128 KB of flash memory, 2 KB of EEPROM, and 32 KB Cache controller Peripheral HUB (PHUB) DMA controller External memory interface (EMIF)
4.1.1 Cortex-M3 Features The Cortex-M3 CPU features include:
4-GB address space. Predefined address regions for code,
data, and peripherals. Multiple buses for efficient and simultaneous accesses of instructions, data, and peripherals.
The Thumb(R)-2 instruction set, which offers ARM-level
sible by all instructions that specify a general purpose register. sible by all 32-bit instructions that specify a general purpose register; they are not accessible by all 16-bit instructions.
performance at Thumb-level code density. This includes 16-bit and 32-bit instructions. Advanced instructions include: Bit-field control Hardware multiply and divide Saturation If-Then Wait for events and interrupts Exclusive access and barrier Special register access The Cortex-M3 does not support ARM instructions.
High Registers: Registers R8-R12 are acces-
R13
Bit-band support. Atomic bit-level write and read operations. Unaligned data storage and access. Contiguous storage of
R13 is the stack pointer register. It is a banked register that switches between two 32-bit stack pointers: the Main Stack Pointer (MSP) and the Process Stack Pointer (PSP). The PSP is used only when the CPU operates at the user level in thread mode. The MSP is used in all other privilege levels and modes. Bits[0:1] of the SP are ignored and considered to be 0, so the SP is always aligned to a word (4 byte) boundary. R14 is the Link Register (LR). The LR stores the return address when a subroutine is called. R15 is the Program Counter (PC). Bit 0 of the PC is ignored and considered to be 0, so instructions are always aligned to a half word (2 byte) boundary. The Program status registers are divided into three status registers, which are accessed either together or separately:
Application Program Status Register (APSR)
data of different byte lengths.
R14 R15
Operation at two privilege levels (privileged and user) and in
two modes (thread and handler). Some instructions can only be executed at the privileged level. There are also two stack pointers: Main (MSP) and Process (PSP). These features support a multitasking operating system running one or more user-level processes.
xPSR
Extensive interrupt and system exception support.
4.1.2 Cortex-M3 Operating Modes The Cortex-M3 operates at either the privileged level or the user level, and in either the thread mode or the handler mode. Because the handler mode is only enabled at the privileged level, there are actually only three states, as shown in Table 4-1. Table 4-1. Operational Level Condition Privileged User Not used Thread mode Running an exception Handler mode Running main program Thread mode
holds program execution status bits such as zero, carry, negative, in bits[27:31].
Interrupt Program Status Register (IPSR)
holds the current exception number in bits[0:8]. holds control bits for interrupt continuable and IF-THEN instructions in bits[10:15] and [25:26]. Bit 24 is always set to 1 to indicate Thumb mode. Trying to clear it causes a fault exception.
Execution Program Status Register (EPSR)
Document Number: 001-55035 Rev. *G
Page 11 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Table 4-2. Cortex M3 CPU Registers (continued) Register PRIMASK Description A 1-bit interrupt mask register. When set, it allows only the nonmaskable interrupt (NMI) and hard fault exception. All other exceptions and interrupts are masked. Table 4-3. PHUB Spokes and Peripherals PHUB Spokes 0 1 2 SRAM IOs, PICU, EMIF PHUB local configuration, Power manager, Clocks, IC, SWV, EEPROM, Flash programming interface Analog interface and trim, Decimator USB, CAN, I2C, Timers, Counters, and PWMs Reserved UDBs group 1 UDBs group 2 Peripherals
FAULTMASK A 1-bit interrupt mask register. When set, it allows only the NMI. All other exceptions and interrupts are masked. BASEPRI A register of up to nine bits that define the masking priority level. When set, it disables all interrupts of the same or higher priority value. If set to 0 then the masking function is disabled. A 2-bit register for controlling the operating mode. Bit 0: 0 = privileged level in thread mode, 1 = user level in thread mode. Bit 1: 0 = default stack (MSP) is used, 1 = alternate stack is used. If in thread mode or user level then the alternate stack is the PSP. There is no alternate stack for handler mode; the bit must be 0 while in handler mode.
3 4 5 6 7
CONTROL
4.3.2 DMA Features
24 DMA channels Each channel has one or more transaction descriptors (TDs)
to configure channel behavior. Up to 128 total TDs can be defined
4.2 Cache Controller
The CY8C53 family has a 1 KB instruction cache between the CPU and the flash memory. This improves instruction execution rate and reduces system power consumption by requiring less frequent flash access.
TDs can be dynamically updated Eight levels of priority per channel Any digitally routable signal, the CPU, or another DMA channel,
can trigger a transaction
Each channel can generate up to two interrupts per transfer Transactions can be stalled or canceled Supports transaction size of infinite or 1 to 64k bytes Large transactions may be broken into smaller bursts of 1 to
4.3 DMA and PHUB
The PHUB and the DMA controller are responsible for data transfer between the CPU and peripherals, and also data transfers between peripherals. The PHUB and DMA also control device configuration during boot. The PHUB consists of:
A central hub that includes the DMA controller, arbiter, and
127 bytes
TDs may be nested and/or chained for complex transactions
router
Multiple spokes that radiate outward from the hub to most
4.3.3 Priority Levels The CPU always has higher priority than the DMA controller when their accesses require the same bus resources. Due to the system architecture, the CPU can never starve the DMA. DMA channels of higher priority (lower priority number) may interrupt current DMA transfers. In the case of an interrupt, the current transfer is allowed to complete its current transaction. To ensure latency limits when multiple DMA accesses are requested simultaneously, a fairness algorithm guarantees an interleaved minimum percentage of bus bandwidth for priority levels 2 through 7. Priority levels 0 and 1 do not take part in the fairness algorithm and may use 100% of the bus bandwidth. If a tie occurs on two DMA requests of the same priority level, a simple round robin method is used to evenly share the allocated bandwidth. The round robin allocation can be disabled for each DMA channel, allowing it to always be at the head of the line. Priority levels 2 to 7 are guaranteed the minimum bus bandwidth shown in Table 4-4 after the CPU and DMA priority levels 0 and 1 have satisfied their requirements. When the fairness algorithm is disabled, DMA access is granted based solely on the priority level; no bus bandwidth guarantees are made.
Page 12 of 102
peripherals
There are two PHUB masters: the CPU and the DMA controller. Both masters may initiate transactions on the bus. The DMA channels can handle peripheral communication without CPU intervention. The arbiter in the central hub determines which DMA channel is the highest priority if there are multiple requests. 4.3.1 PHUB Features
CPU and DMA controller are both bus masters to the PHUB Eight Multi-layer AHB Bus parallel access paths (spokes) for
peripheral access different spokes
Simultaneous CPU and DMA access to peripherals located on Simultaneous DMA source and destination burst transactions
on different spokes
Supports 8-, 16-, 24-, and 32-bit addressing and data
Document Number: 001-55035 Rev. *G
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Table 4-4. Priority Levels Priority Level 0 1 2 3 4 5 6 7 % Bus Bandwidth 100.0 100.0 50.0 25.0 12.5 6.2 3.1 1.5
4.3.4.6 Scatter Gather DMA In the case of scatter gather DMA, there are multiple noncontiguous sources or destinations that are required to effectively carry out an overall DMA transaction. For example, a packet may need to be transmitted off of the device and the packet elements, including the header, payload, and trailer, exist in various noncontiguous locations in memory. Scatter gather DMA allows the segments to be concatenated together by using multiple TDs in a chain. The chain gathers the data from the multiple locations. A similar concept applies for the reception of data onto the device. Certain parts of the received data may need to be scattered to various locations in memory for software processing convenience. Each TD in the chain specifies the location for each discrete element in the chain. 4.3.4.7 Packet Queuing DMA Packet queuing DMA is similar to scatter gather DMA but specifically refers to packet protocols. With these protocols, there may be separate configuration, data, and status phases associated with sending or receiving a packet. For instance, to transmit a packet, a memory mapped configuration register can be written inside a peripheral, specifying the overall length of the ensuing data phase. The CPU can set up this configuration information anywhere in system memory and copy it with a simple TD to the peripheral. After the configuration phase, a data phase TD (or a series of data phase TDs) can begin (potentially using scatter gather). When the data phase TD(s) finish, a status phase TD can be invoked that reads some memory mapped status information from the peripheral and copies it to a location in system memory specified by the CPU for later inspection. Multiple sets of configuration, data, and status phase "subchains" can be strung together to create larger chains that transmit multiple packets in this way. A similar concept exists in the opposite direction to receive the packets. 4.3.4.8 Nested DMA One TD may modify another TD, as the TD configuration space is memory mapped similar to any other peripheral. For example, a first TD loads a second TD's configuration and then calls the second TD. The second TD moves data as required by the application. When complete, the second TD calls the first TD, which again updates the second TD's configuration. This process repeats as often as necessary.
4.3.4 Transaction Modes Supported The flexible configuration of each DMA channel and the ability to chain multiple channels allow the creation of both simple and complex use cases. General use cases include, but are not limited to: 4.3.4.1 Simple DMA In a simple DMA case, a single TD transfers data between a source and sink (peripherals or memory location). 4.3.4.2 Auto Repeat DMA Auto repeat DMA is typically used when a static pattern is repetitively read from system memory and written to a peripheral. This is done with a single TD that chains to itself. 4.3.4.3 Ping Pong DMA A ping pong DMA case uses double buffering to allow one buffer to be filled by one client while another client is consuming the data previously received in the other buffer. In its simplest form, this is done by chaining two TDs together so that each TD calls the opposite TD when complete. 4.3.4.4 Circular DMA Circular DMA is similar to ping pong DMA except it contains more than two buffers. In this case there are multiple TDs; after the last TD is complete it chains back to the first TD. 4.3.4.5 Indexed DMA In an indexed DMA case, an external master requires access to locations on the system bus as if those locations were shared memory. As an example, a peripheral may be configured as an SPI or I2C slave where an address is received by the external master. That address becomes an index or offset into the internal system bus memory space. This is accomplished with an initial "address fetch" TD that reads the target address location from the peripheral and writes that value into a subsequent TD in the chain. This modifies the TD chain on the fly. When the "address fetch" TD completes it moves on to the next TD, which has the new address information embedded in it. This TD then carries out the data transfer with the address location required by the external master.
Document Number: 001-55035 Rev. *G
Page 13 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
4.4 Interrupt Controller
The Cortex-M3 NVIC supports 16 system exceptions and 32 interrupts from peripherals, as shown in Table 4-5. Table 4-5. Cortex-M3 Exceptions and Interrupts Exception Number 1 2 3 Exception Type Reset NMI Hard fault Priority -3 (highest) -2 -1 Exception Table Address Offset 0x00 0x04 0x08 0x0C Function Starting value of R13 / MSP Reset Non maskable interrupt All classes of fault, when the corresponding fault handler cannot be activated because it is currently disabled or masked Memory management fault, for example, instruction fetch from a nonexecutable region Error response received from the bus system; caused by an instruction prefetch abort or data access error Typically caused by invalid instructions or trying to switch to ARM mode Reserved System service call via SVC instruction Debug monitor Reserved Deferred request for system service System tick timer Peripheral interrupt request #0 - #31
4 5 6 7 - 10 11 12 13 14 15 16 - 47
MemManage Bus fault Usage fault - SVC Debug monitor - PendSV SYSTICK IRQ
Programmable Programmable Programmable - Programmable Programmable - Programmable Programmable Programmable
0x10 0x14 0x18 0x1C - 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 - 0x3FC
Bit 0 of each exception vector indicates whether the exception is executed using ARM or Thumb instructions. Because the Cortex-M3 only supports Thumb instructions, this bit must always be 1. The Cortex-M3 non maskable interrupt (NMI) input can be routed to any pin, via the DSI, or disconnected from all pins. See "DSI Routing Interface Description" section on page 42. The NVIC handles interrupts from the peripherals, and passes the interrupt vectors to the CPU. It is closely integrated with the CPU for low latency interrupt handling. Features include:
32 interrupts. Multiple sources for each interrupt. Configurable number of priority levels: from 3 to 8. Dynamic reprioritization of interrupts. Priority grouping. This allows selection of preempting and non
Support for tail-chaining, and late arrival, of interrupts. This
enables back-to-back interrupt processing without the overhead of state saving and restoration between interrupts. restored on interrupt exit, with no instruction overhead.
Processor state automatically saved on interrupt entry, and
preempting interrupt levels.
If the same priority level is assigned to two or more interrupts, the interrupt with the lower vector number is executed first. Each interrupt vector may choose from three interrupt sources: Fixed Function, DMA, and UDB. The fixed function interrupts are direct connections to the most common interrupt sources and provide the lowest resource cost connection. The DMA interrupt sources provide direct connections to the two DMA interrupt sources provided per DMA channel. The third interrupt source for vectors is from the UDB digital routing array. This allows any digital signal available to the UDB array to be used as an interrupt source. All interrupt sources may be routed to any interrupt vector using the UDB interrupt source connections.
Document Number: 001-55035 Rev. *G
Page 14 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Table 4-6. Interrupt Vector Table Interrupt # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Cortex-M3 Exception # 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Fixed Function Low voltage detect (LVD) Cache/ECC Reserved Sleep (Pwr Mgr) PICU[0] PICU[1] PICU[2] PICU[3] PICU[4] PICU[5] PICU[6] PICU[12] PICU[15] Comparators Combined Switched Caps Combined I2C CAN Timer/Counter0 Timer/Counter1 Timer/Counter2 Timer/Counter3 USB SOF Int USB Arb Int USB Bus Int USB Endpoint[0] USB Endpoint Data Reserved Reserved Reserved Decimator Int phub_err_int eeprom_fault_int DMA phub_termout0[0] phub_termout0[1] phub_termout0[2] phub_termout0[3] phub_termout0[4] phub_termout0[5] phub_termout0[6] phub_termout0[7] phub_termout0[8] phub_termout0[9] phub_termout0[10] phub_termout0[11] phub_termout0[12] phub_termout0[13] phub_termout0[14] phub_termout0[15] phub_termout1[0] phub_termout1[1] phub_termout1[2] phub_termout1[3] phub_termout1[4] phub_termout1[5] phub_termout1[6] phub_termout1[7] phub_termout1[8] phub_termout1[9] phub_termout1[10] phub_termout1[11] phub_termout1[12] phub_termout1[13] phub_termout1[14] phub_termout1[15] UDB udb_intr[0] udb_intr[1] udb_intr[2] udb_intr[3] udb_intr[4] udb_intr[5] udb_intr[6] udb_intr[7] udb_intr[8] udb_intr[9] udb_intr[10] udb_intr[11] udb_intr[12] udb_intr[13] udb_intr[14] udb_intr[15] udb_intr[16] udb_intr[17] udb_intr[18] udb_intr[19] udb_intr[20] udb_intr[21] udb_intr[22] udb_intr[23] udb_intr[24] udb_intr[25] udb_intr[26] udb_intr[27] udb_intr[28] udb_intr[29] udb_intr[30] udb_intr[31]
Document Number: 001-55035 Rev. *G
Page 15 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
5. Memory
5.1 Static RAM
CY8C53 static RAM (SRAM) is used for temporary data storage. Code can be executed at full speed from the portion of SRAM that is located in the code space. This process is slower from SRAM above 0x20000000. The device provides up to 64 KB of SRAM. The CPU or the DMA controller can access all of SRAM. The SRAM can be accessed simultaneously by the Cortex-M3 CPU and the DMA controller if accessing different 32-KB blocks.
how to take full advantage of the security features in PSoC, see the PSoC 5 TRM. Table 5-1. Flash Protection Protection Setting Unprotected Factory Upgrade Allowed External read and write - + internal read and write External write + internal read and write External read External read and write External read and write + internal write Not Allowed
5.2 Flash Program Memory
Flash memory in PSoC devices provides nonvolatile storage for user firmware, user configuration data, bulk data storage, and optional ECC data. The main flash memory area contains up to 256 KB of user program space. Up to an additional 32 KB of flash space is available for Error Correcting Codes (ECC). If ECC is not used this space can store device configuration data and bulk user data. User code may not be run out of the ECC flash memory section. ECC can correct one bit error and detect two bit errors per 8 bytes of firmware memory; an interrupt can be generated when an error is detected. The flash output is 9 bytes wide with 8 bytes of data and 1 byte of ECC data. The CPU or DMA controller read both user code and bulk data located in flash through the cache controller. This provides higher CPU performance. If ECC is enabled, the cache controller also performs error checking and correction. Flash programming is performed through a special interface and preempts code execution out of flash. Code execution out of cache may continue during flash programming as long as that code is contained inside the cache. The flash programming interface performs flash erasing, programming and setting code protection levels. Flash In System Serial Programming (ISSP), typically used for production programming, is possible through both the SWD and JTAG interfaces. In-system programming, typically used for bootloaders, is also possible using serial interfaces such as I2C, USB, UART, and SPI, or any communications protocol.
Field Upgrade Internal read and write Full Protection Internal read
Disclaimer Note the following details of the flash code protection features on Cypress devices. Cypress products meet the specifications contained in their particular Cypress datasheets. Cypress believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Cypress is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress are committed to continuously improving the code protection features of our products.
5.4 EEPROM
PSoC EEPROM memory is a byte addressable nonvolatile memory. The CY8C53 has 2 KB of EEPROM memory to store user data. Reads from EEPROM are random access at the byte level. Reads are done directly; writes are done by sending write commands to an EEPROM programming interface. CPU code execution can continue from flash during EEPROM writes. EEPROM is erasable and writeable at the row level. The EEPROM is divided into two sections, each containing 64 rows of 16 bytes each. The CPU can not execute out of EEPROM. There is no ECC hardware associated with EEPROM. If ECC is required it must be handled in firmware.
5.3 Flash Security
All PSoC devices include a flexible flash protection model that prevents access and visibility to on-chip flash memory. This prevents duplication or reverse engineering of proprietary code. Flash memory is organized in blocks, where each block contains 256 bytes of program or data and 32 bytes of ECC or configuration data. The device offers the ability to assign one of four protection levels to each row of flash. Table 5-1 lists the protection modes available. Flash protection levels can only be changed by performing a complete flash erase. The Full Protection and Field Upgrade settings disable external access (through a debugging tool such as PSoC Creator, for example). If your application requires code update through a boot loader, then use the Field Upgrade setting. Use the Unprotected setting only when no security is needed in your application. The PSoC device also offers an advanced security feature called Device Security which permanently disables all test, programming, and debug ports, protecting your application from external access (see the "Device Security" section on page 57). For more information on
Document Number: 001-55035 Rev. *G
5.5 External Memory Interface
CY8C53 provides an EMIF for connecting to external memory devices. The connection allows read and write accesses to external memories. The EMIF operates in conjunction with UDBs, I/O ports, and other hardware to generate external memory address and control signals. At 33 MHz, each memory access cycle takes four bus clock cycles. Figure 5-1 is the EMIF block diagram. The EMIF supports synchronous and asynchronous memories. The CY8C53 only supports one type of external memory device at a time.
Page 16 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
External memory is located in the Cortex-M3 external RAM space; it can use up to 24 address bits. See Memory Map on page 18. The memory can be 8 or 16 bits wide. Cortex-M3 instructions can be fetched/executed from external memory, although at a slower rate than from flash. Figure 5-1. EMIF Block Diagram
Address Signals
External MEM_ ADDR[23:0] _ I/O PORTs
Data, Address, and Control Signals
IO IF
Data Signals
External MEM_ DATA[15:0] _ I/O PORTs
Control Signals
PHUB
Data, Address, and Control Signals
I/O PORTs
Control
DSI Dynamic Output Control
UDB
DSI to Port
Data, Address, and Control Signals
EM Control Signals
Other Control Signals
EMIF
Document Number: 001-55035 Rev. *G
Page 17 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
5.6 Memory Map
The Cortex-M3 has a fixed address map, which allows peripherals to be accessed by simple memory access instructions. 5.6.1 Address Map The 4-GB address space is divided into the ranges shown in Table 5-2: Table 5-2. Address Map Address Range 0x00000000 - 0x1FFFFFFF Size 0.5 GB Use Program code. This includes the exception vector table at power up, which starts at address 0. Static RAM. This includes a 1 MByte bit-band region starting at 0x20000000 and a 32 Mbyte bit-band alias region starting at 0x22000000. Peripherals. This includes a 1 MByte bit-band region starting at 0x40000000 and a 32 Mbyte bit-band alias region starting at 0x42000000. External RAM. External peripherals. Internal peripherals, including the NVIC and debug and trace modules.
Table 5-3. Peripheral Data Address Map (continued) Address Range 0x40004900 - 0x400049FF I 2C 0x40004E00 - 0x40004EFF Decimator 0x40004F00 - 0x40004FFF Fixed timer/counter/PWMs 0x40005000 - 0x400051FF I/O ports control 0x40005400 - 0x400054FF External Memory Interface (EMIF) control registers 0x40005800 - 0x40005FFF Analog Subsystem Interface 0x40006000 - 0x400060FF USB Controller 0x40006400 - 0x40006FFF UDB Configuration 0x40007000 - 0x40007FFF PHUB Configuration 0x40008000 - 0x400087FF EEPROM 0x4000A000 - 0x4000A400 CAN 0x40010000 - 0x4001FFFF Digital Interconnect Configuration 0x48000000 - 0x48007FFF Flash ECC Bytes 0x60000000 - 0x60FFFFFF External Memory Interface (EMIF) 0xE0000000 - 0xE00FFFFF Cortex-M3 PPB Registers, including NVIC, debug, and trace Purpose controller
0x20000000 - 0x3FFFFFFF
0.5 GB
0x40000000 - 0x5FFFFFFF
0.5 GB
0x60000000 - 0x9FFFFFFF 0xA0000000 - 0xDFFFFFFF 0xE0000000 - 0xFFFFFFFF
1 GB 1 GB 0.5 GB
The bit-band feature allows individual bits in words in the bit-band region to be read or written as atomic operations. This is done by reading or writing bit 0 of corresponding words in the bit-band alias region. For example, to set bit 3 in the word at address 0x20000000, write a 1 to address 0x2200000C. To test the value of that bit, read address 0x2200000C and the result is either 0 or 1 depending on the value of the bit. Most memory accesses done by the Cortex-M3 are aligned, that is, done on word (4-byte) boundary addresses. Unaligned accesses of words and 16-bit half-words on nonword boundary addresses can also be done, although they are less efficient. 5.6.2 Address Map and Cortex-M3 Buses The ICode and DCode buses are used only for accesses within the Code address range, 0 - 0x1FFFFFFF. The system bus is used for data accesses and debug accesses within the ranges 0x20000000 - 0xDFFFFFFF and 0xE0100000 - 0xFFFFFFFF. Instruction fetches can also be done within the range 0x20000000 - 0x3FFFFFFF, although these can be slower than instruction fetches via the ICode bus. The private peripheral bus (PPB) is used within the Cortex-M3 to access system control registers and debug and trace module registers.
Table 5-3. Peripheral Data Address Map Address Range 0x00000000 - 0x0003FFFF 256K Flash 0x1FFF8000 - 0x1FFFFFFF 32K SRAM in Code region 0x20000000 - 0x20007FFF 32K SRAM in SRAM region 0x40004000 - 0x400042FF Clocking, PLLs, and oscillators 0x40004300 - 0x400043FF Power management 0x40004500 - 0x400045FF Ports interrupt control 0x40004700 - 0x400047FF Flash programming interface 0x40004800 - 0x400048FF Cache controller Purpose
Document Number: 001-55035 Rev. *G
Page 18 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
6. System Integration
6.1 Clocking System
The clocking system generates, divides, and distributes clocks throughout the PSoC system. For the majority of systems, no external crystal is required. The IMO and PLL together can generate up to a 80-MHz clock, accurate to 1% over voltage and temperature. Additional internal and external clock sources allow each design to optimize accuracy, power, and cost. All of the system clock sources can be used to generate other clock frequencies in the 16-bit clock dividers and UDBs for anything the user wants, for example a UART baud rate generator. Clock generation and distribution is automatically configured through the PSoC Creator IDE graphical interface. This is based on the complete system's requirements. It greatly speeds the design process. PSoC Creator allows designers to build clocking systems with minimal input. The designer can specify desired clock frequencies and accuracies, and the software locates or builds a clock that meets the required specifications. This is possible because of the programmability inherent PSoC.
Key features of the clocking system include:
Seven general purpose clock sources
3- to 74-MHz IMO, 1% at 3 MHz 4- to 33-MHz external crystal oscillator (MHzECO) Clock doubler provides a doubled clock frequency output for the USB block, see USB Clock Domain on page 22 DSI signal from an external I/O pin or other logic 24- to 80-MHz fractional PLL sourced from IMO, MHzECO, or DSI Clock doubler 1-kHz, 33-kHz, 100-kHz ILO for watchdog timer (WDT) and sleep timer 32.768-kHz external crystal oscillator (kHzECO) for RTC

IMO has a USB mode that auto locks to USB bus clock requiring
no external crystal for USB. (USB equipped parts only)
Independently sourced clock dividers in all clocks Eight 16-bit clock dividers for the digital system Four 16-bit clock dividers for the analog system Dedicated 16-bit divider for the CPU bus and CPU clock Automatic clock configuration in PSoC Creator
Table 6-1. Oscillator Summary Source IMO MHzECO DSI PLL Doubler ILO kHzECO Fmin 3 MHz 4 MHz 0 MHz 24 MHz 12 MHz 1 kHz 32 kHz Tolerance at Fmin 1% over voltage and temperature Crystal dependent Input dependent Input dependent Input dependent -50%, +100% Crystal dependent Fmax 74 MHz 33 MHz 66 MHz 80 MHz 48 MHz 100 kHz 32 kHz Tolerance at Fmax 7% Crystal dependent Input dependent Input dependent Input dependent -55%, +100% Crystal dependent Startup Time 10 s max 5 ms typ, max is crystal dependent Input dependent 250 s max 1 s max 15 ms max in lowest power mode 500 ms typ, max is crystal dependent
Document Number: 001-55035 Rev. *G
Page 19 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Figure 6-1. Clocking Subsystem
3-74 MHz IMO
4-33 MHz ECO
External IO or DSI 0-66 MHz
32 kHz ECO
1,33,100 kHz ILO
12-48 MHz Doubler
CPU Clock
24-80 MHz PLL
System Clock Mux Bus Clock Divider 16 bit
s k e w s k e w s k e w s k e w
Bus Clock
Digital Clock Divider 16 bit
Digital Clock Divider 16 bit
Analog Clock Divider 16 bit
Digital Clock Divider 16 bit 7
Digital Clock Divider 16 bit 7
Analog Clock Divider 16 bit
Digital Clock Divider 16 bit
Digital Clock Divider 16 bit
Analog Clock Divider 16 bit
Digital Clock Divider 16 bit
Digital Clock Divider 16 bit
Analog Clock Divider 16 bit
6.1.1 Internal Oscillators 6.1.1.1 Internal Main Oscillator In most designs the IMO is the only clock source required, due to its 1% accuracy. The IMO operates with no external components and outputs a stable clock. A factory trim for each frequency range is stored in the device. With the factory trim, tolerance varies from 1% at 3 MHz, up to 7% at 74 MHz. The IMO, in conjunction with the PLL, allows generation of CPU and system clocks up to the device's maximum frequency (see Phase-Locked Loop) The IMO provides clock outputs at 3-, 6-, 12-, 24-, 48-, and 74-MHz. 6.1.1.2 Clock Doubler The clock doubler outputs a clock at twice the frequency of the input clock. The doubler works for input frequency ranges of 6 to 24 MHz (providing 12 to 48 MHz at the output). It can be configured to use a clock from the IMO, MHzECO, or the DSI (external pin). The doubler is typically used to clock the USB. 6.1.1.3 Phase-Locked Loop The PLL allows low frequency, high accuracy clocks to be multiplied to higher frequencies. This is a tradeoff between higher clock frequency and accuracy and, higher power consumption and increased startup time.
The PLL block provides a mechanism for generating clock frequencies based upon a variety of input sources. The PLL outputs clock frequencies in the range of 24 to 80 MHz. Its input and feedback dividers supply 4032 discrete ratios to create almost any desired system clock frequency. The accuracy of the PLL output depends on the accuracy of the PLL input source. The most common PLL use is to multiply the IMO clock at 3 MHz, where it is most accurate, to generate the CPU and system clocks up to the device's maximum frequency. The PLL achieves phase lock within 250 s (verified by bit setting). It can be configured to use a clock from the IMO, MHzECO, or DSI (external pin). The PLL clock source can be used until lock is complete and signaled with a lock bit. The lock signal can be routed through the DSI to generate an interrupt. Disable the PLL before entering low power modes. 6.1.1.4 Internal Low Speed Oscillator The ILO provides clock frequencies for low power consumption, including the watchdog timer, and sleep timer. The ILO generates up to three different clocks: 1 kHz, 33 kHz, and 100 kHz. The 1-kHz clock (CLK1K) is typically used for a background `heartbeat' timer. This clock inherently lends itself to low power supervisory operations such as the watchdog timer and long sleep intervals using the central timewheel (CTW).
Document Number: 001-55035 Rev. *G
Page 20 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
The central timewheel is a 1-kHz, free-running, 13-bit counter clocked by the ILO. The central timewheel is always enabled except in hibernate mode and when the CPU is stopped during debug on chip mode. It can be used to generate periodic interrupts for timing purposes or to wake the system from a low power mode. Firmware can reset the central timewheel. The central timewheel can be programmed to wake the system periodically and optionally issue an interrupt. This enables flexible, periodic wakeups from low power modes or coarse timing applications. Systems that require accurate timing should use the RTC capability instead of the central timewheel. The 100-kHz clock (CLK100K) works as a low-power system clock to run the CPU. It can also generate time intervals such as fast sleep intervals using the fast timewheel. The fast timewheel is a 100 kHz, 5-bit counter clocked by the ILO that can also be used to wake the system. The fast timewheel settings are programmable, and the counter automatically resets when the terminal count is reached. This enables flexible, periodic wakeups of the CPU at a higher rate than is allowed using the central timewheel. The fast timewheel can generate an optional interrupt each time the terminal count is reached. The 33-kHz clock (CLK33K) comes from a divide-by-3 operation on CLK100K. This output can be used as a reduced accuracy version of the 32.768-kHz ECO clock with no need for a crystal. 6.1.2 External Oscillators 6.1.2.1 MHz External Crystal Oscillator The MHzECO provides high frequency, high precision clocking using an external crystal (see Figure 6-2). It supports a wide variety of crystal types, in the range of 4 to 33 MHz. When used in conjunction with the PLL, it can generate CPU and system clocks up to the device's maximum frequency (see Phase-Locked Loop on page 20). The GPIO pins connecting to the external crystal and capacitors are fixed. MHzECO accuracy depends on the crystal chosen. Figure 6-2. MHzECO Block Diagram
6.1.2.2 32.768 kHz ECO The 32.768-kHz external crystal oscillator (32kHzECO) provides precision timing with minimal power consumption using an external 32.768-kHz watch crystal (see Figure 6-3). The 32kHzECO also connects directly to the sleep timer and provides the source for the RTC. The RTC uses a 1-second interrupt to implement the RTC functionality in firmware. The oscillator works in two distinct power modes. This allows users to trade off power consumption with noise immunity from neighboring circuits. The GPIO pins connected to the external crystal and capacitors are fixed. Figure 6-3. 32kHzECO Block Diagram
32 kHz Crystal Osc
XCLK32K
Xi (Pin P15[3]) External Components
Xo (Pin P15[2]) 32 kHz crystal Capacitors
6.1.2.3 Digital System Interconnect The DSI provides routing for clocks taken from external clock oscillators connected to I/O. The oscillators can also be generated within the device in the digital system and Universal Digital Blocks. While the primary DSI clock input provides access to all clocking resources, up to eight other DSI clocks (internally or externally generated) may be routed directly to the eight digital clock dividers. This is only possible if there are multiple precision clock sources.
4 - 33 MHz Crystal Osc
XCLK_MHZ
Xi (Pin P15[1]) External Components
Xo (Pin P15[0]) 4 - 33 MHz crystal Capacitors
Document Number: 001-55035 Rev. *G
Page 21 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
6.1.3 Clock Distribution All seven clock sources are inputs to the central clock distribution system. The distribution system is designed to create multiple high precision clocks. These clocks are customized for the design's requirements and eliminate the common problems found with limited resolution prescalers attached to peripherals. The clock distribution system generates several types of clock trees.
The system clock is used to select and supply the fastest clock
Each clock divider consists of an 8-input multiplexer, a 16-bit clock divider (divide by 2 and higher) that generates ~50% duty cycle clocks, system clock resynchronization logic, and deglitch logic. The outputs from each digital clock tree can be routed into the digital system interconnect and then brought back into the clock system as an input, allowing clock chaining of up to 32 bits. 6.1.4 USB Clock Domain The USB clock domain is unique in that it operates largely asynchronously from the main clock network. The USB logic contains a synchronous bus interface to the chip, while running on an asynchronous clock to process USB data. The USB logic requires a 48 MHz frequency. This frequency can be generated from different sources, including DSI clock at 48 MHz or doubled value of 24 MHz from internal oscillator, DSI signal, or crystal oscillator.
in the system for general system clock requirements and clock synchronization of the PSoC device. system's bus clock used for data transfers and the CPU. The CPU clock is directly derived from the bus clock.
Bus clock 16-bit divider uses the system clock to generate the
Eight fully programmable 16-bit clock dividers generate digital
system clocks for general use in the digital system, as configured by the design's requirements. Digital system clocks can generate custom clocks derived from any of the seven clock sources for any purpose. Examples include baud rate generators, accurate PWM periods, and timer clocks, and many others. If more than eight digital clock dividers are required, the UDBs and fixed function timer/counter/PWMs can also generate clocks. components that require clocking, such as the ADC. The analog clock dividers include skew control to ensure that critical analog events do not occur simultaneously with digital switching events. This is done to reduce analog system noise.
Four 16-bit clock dividers generate clocks for the analog system
Document Number: 001-55035 Rev. *G
Page 22 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
6.2 Power System
The power system consists of separate analog, digital, and I/O supply pins, labeled VDDA, VDDD, and Vddiox, respectively. It also includes two internal 1.8 V regulators that provide the digital (VCCD) and analog (VCCA) supplies for the internal core logic. The output pins of the regulators (VCCD and VCCA) and the VDDIO pins must have capacitors connected as shown in Figure 6-4. The two VCCD pins must be shorted together, with as short a trace as possible, and connected to a 1 F 10% X5R capacitor. The power system also contains a sleep regulator, an I2C regulator, and a hibernate regulator. Figure 6-4. PSoC Power System
Vddio2 1 F Vddd Vddio0
0.1 F Vddd Vccd Vssd Vddio2 I/O Supply
0.1 F I/O Supply Vddio0
I2C Regulator
0.1 F
Digital Domain
Sleep Regulator
Vdda Vdda
Vssd
Digital Regulators
Analog Regulator
Vcca 1 F Vssa
0.1 F .
Analog Domain
Hibernate Regulator
Vddio1 Vccd I/O Supply Vddd Vssd I/O Supply Vddio3 Vddio3
0.1F 0.1 F Vddio1 Vddd
0.1 F
Note The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended, as shown in Figure 2-5. 6.2.1 Power Modes PSoC 5 devices have four different power modes, as shown in Table 6-2 and Table 6-3. The power modes allow a design to easily provide required functionality and processing power while simultaneously minimizing power consumption and maximizing battery life in low power and portable devices. PSoC 5 power modes, in order of decreasing power consumption are:
Active Alternate Active Sleep Hibernate
Document Number: 001-55035 Rev. *G Page 23 of 102
Active is the main processing mode. Its functionality is configurable. Each power controllable subsystem is enabled or disabled by using separate power configuration template registers. In alternate active mode, fewer subsystems are enabled, reducing power. In sleep mode most resources are disabled regardless of the template settings. Sleep mode is optimized to provide timed sleep intervals and Real Time Clock functionality. The lowest power mode is hibernate, which retains register and SRAM state, but no clocks, and allows wakeup only from I/O pins. Figure 6-5 illustrates the allowable transitions between power modes.
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Table 6-2. Power Modes Power Modes Active Description Entry Condition Wakeup Source Any interrupt Active Clocks Regulator
Primary mode of operation, all Wakeup, reset, peripherals available manual register (programmable) entry
Any (programmable) All regulators available. Digital and analog regulators can be disabled if external regulation used. Any (programmable) All regulators available. Digital and analog regulators can be disabled if external regulation used.
Alternate Active
Similar to Active mode, and is Manual register typically configured to have entry fewer peripherals active to reduce power. One possible configuration is to turn off the CPU and flash, and run peripherals at full speed All subsystems automatically disabled Manual register entry
Any interrupt
Sleep
Comparator, ILO/kHzECO PICU, I2C, RTC, CTW, LVD
Both digital and analog regulators buzzed. Digital and analog regulators can be disabled if external regulation used. Only hibernate regulator active.
Hibernate
All subsystems automatically disabled Lowest power consuming mode with all peripherals and internal regulators disabled, except hibernate regulator is enabled Configuration and memory contents retained
Manual register entry
PICU
Table 6-3. Power Modes Wakeup Time and Power Consumption Sleep Modes Active Alternate Active Sleep Wakeup Time - - <15 s Current (Typ) 2 mA[7] TBD 2 A 300 nA Code Digital Execution Resources Yes User defined No No All All I 2C None Analog Resources All All Clock Sources Available All All Wakeup Sources - - Reset Sources All All
Comparator ILO/kHzECO None None
Comparator, PICU, XRES, LVD, I2C, RTC, CTW, LVD WDR PICU XRES
Hibernate <100 s
Document Number: 001-55035 Rev. *G
Page 24 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Figure 6-5. Power Mode Transitions
Active
6.2.1.5 Wakeup Events Wakeup events are configurable and can come from an interrupt or device reset. A wakeup event restores the system to active mode. Interrupt sources include internally generated interrupts, power supervisor, central timewheel, and I/O interrupts. Internal interrupt sources can come from a variety of peripherals, such as analog comparators and UDBs. The central timewheel provides periodic interrupts to allow the system to wake up, poll peripherals, or perform real-time functions. Reset event sources include the external reset I/O pin (XRES), WDT, and Precision Reset (PRES). 6.2.2 Boost Converter Applications that use a supply voltage of less than 1.71 V, such as solar or single cell battery supplies, may use the on-chip boost converter. The boost converter may also be used in any system that requires a higher operating voltage than the supply provides. For instance, this includes driving 5.0 V LCD glass in a 3.3 V system. The boost converter accepts an input voltage as low as 0.5 V. With one low cost inductor it produces a selectable output voltage sourcing enough current to operate the PSoC and other on-board components. The boost converter accepts an input voltage from 0.5 V to 5.5 V (VBAT), and can start up with VBAT as low as 0.5 V. The converter provides a user configurable output voltage of 1.8 to 5.0 V (VBOOST). VBAT is typically less than VBOOST; if VBAT is greater than or equal to VBOOST, then VBOOST will be the same as VBAT. The block can deliver up to 50 mA (IBOOST) depending on configuration. Four pins are associated with the boost converter: VBAT, VSSB, VBOOST, and Ind. The boosted output voltage is sensed at the VBOOST pin and must be connected directly to the chip's supply inputs. An inductor is connected between the VBAT and Ind pins. The designer can optimize the inductor value to increase the boost converter efficiency based on input voltage, output voltage, current and switching frequency. The External Schottky diode shown in Figure 6-6 is required only in cases when VBOOST>3.6 V. Figure 6-6. Application for Boost Converter
Manual Sleep Hibernate
Buzz Alternate Active
6.2.1.1 Active Mode Active mode is the primary operating mode of the device. When in active mode, the active configuration template bits control which available resources are enabled or disabled. When a resource is disabled, the digital clocks are gated, analog bias currents are disabled, and leakage currents are reduced as appropriate. User firmware can dynamically control subsystem power by setting and clearing bits in the active configuration template. The CPU can disable itself, in which case the CPU is automatically reenabled at the next wakeup event. When a wakeup event occurs, the global mode is always returned to active, and the CPU is automatically enabled, regardless of its template settings. Active mode is the default global power mode upon boot. 6.2.1.2 Alternate Active Mode Alternate Active mode is very similar to active mode. In alternate active mode, fewer subsystems are enabled, to reduce power consumption. One possible configuration is to turn off the CPU and flash, and run peripherals at full speed. 6.2.1.3 Sleep Mode Sleep mode reduces power consumption when a resume time of 15 s is acceptable. The wake time is used to ensure that the regulator outputs are stable enough to directly enter active mode. 6.2.1.4 Hibernate Mode In hibernate mode nearly all of the internal functions are disabled. Internal voltages are reduced to the minimal level to keep vital systems alive. Configuration state is preserved in hibernate mode and SRAM memory is retained. GPIOs configured as digital outputs maintain their previous values and external GPIO pin interrupt settings are preserved. The device can only return from hibernate mode in response to an external I/O interrupt. The resume time from hibernate mode is less than 100 s.
Optional Schottky Diode. Only required when Vdd >3.6 V.
Vboost Vdda Vddd
IND PSoC 10 H 22 F 0.1 F
22 F
Vbat Vssb Vssa Vssd
Note 7. IMO 6 MHz, CPU 6 MHz, all peripherals disabled Document Number: 001-55035 Rev. *G Page 25 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
The boost converter can be operated in two different modes: active and standby. Active mode is the normal mode of operation where the boost regulator actively generates a regulated output voltage. In standby mode, most boost functions are disabled, thus reducing power consumption of the boost circuit. The converter can be configured to provide low power, low current regulation in the standby mode. The external 32 kHz crystal can be used to generate inductor boost pulses on the rising and falling edge of the clock when the output voltage is less than the programmed value. This is called automatic thump mode (ATM). The boost typically draws 200 A in active mode and 12 A in standby mode. The boost operating modes must be used in conjunction with chip power modes to minimize the total chip power consumption. Table 6-4 lists the boost power modes available in different chip power modes. Table 6-4. Chip and Boost Power Modes Compatibility
Chip Power Modes Chip -Active mode Chip -Sleep mode Boost Power Modes Boost can be operated in either active or standby mode. Boost can be operated in either active or standby mode. However, it is recommended to operate boost in standby mode for low power consumption Boost can only be operated in active mode. However, it is recommended not to use boost in chip hibernate mode due to high current consumption in boost active mode
Figure 6-7. Resets
Vddd Vdda
Power Voltage Level Monitors Reset Pin
Processor Interrupt
External Reset
Reset Controller
System Reset
Watchdog Timer
Software Reset Register
Chip-Hibernate mode
The term system reset indicates that the processor as well as analog and digital peripherals and registers are reset. A reset status register holds the source of the most recent reset or power voltage monitoring interrupt. The program may examine this register to detect and report exception conditions. This register is cleared after a power on reset. 6.3.1 Reset Sources 6.3.1.1 Power Voltage Level Monitors
IPOR - Initial Power on Reset
The switching frequency can be set to 100 kHz, 400 kHz, 2 MHz, or 32 kHz to optimize efficiency and component cost. The 100 kHz, 400 kHz, and 2 MHz switching frequencies are generated using oscillators internal to the boost converter block. When the 32 kHz switching frequency is selected, the clock is derived from a 32 kHz external crystal oscillator. The 32 kHz external clock is primarily intended for boost standby mode. If the boost converter is not used in a given application, tie the VBAT, VSSB, and VBOOST pins to ground and leave the Ind pin unconnected.
6.3 Reset
CY8C53 has multiple internal and external reset sources available. The reset sources are:
Power source monitoring - The analog and digital power
voltages, VDDA, VDDD, VCCA, and VCCD are monitored in several different modes during power up, active mode, and sleep mode (buzzing). If any of the voltages goes outside predetermined ranges then a reset is generated. The monitors are programmable to generate an interrupt to the processor under certain conditions before reaching the reset thresholds. pulling the reset pin (XRES) low. The XRES pin includes an internal pull-up to Vddio1. VDDD, VDDA, and Vddio1 must all have voltage applied before the part comes out of reset.
At initial power on, IPOR monitors the power voltages VDDD and VDDA, both directly at the pins and at the outputs of the corresponding internal regulators. The trip level is not precise. It is set to approximately 1 volt, which is below the lowest specified operating voltage but high enough for the internal circuits to be reset and to hold their reset state. The monitor generates a reset pulse that is at least 100 ns wide. It may be much wider if one or more of the voltages ramps up slowly. To save power the IPOR circuit is disabled when the internal digital supply is stable. Voltage supervision is then handed off to the precise low voltage reset (PRES) circuit. When the voltage is high enough for PRES to release, the IMO starts.
PRES - Precise Low Voltage Reset
External - The device can be reset from an external source by
Watchdog timer - A watchdog timer monitors the execution of
This circuit monitors the outputs of the analog and digital internal regulators after power up. The regulator outputs are compared to a precise reference voltage. The response to a PRES trip is identical to an IPOR reset.
instructions by the processor. If the watchdog timer is not reset by firmware within a certain period of time, the watchdog timer generates a reset.
Software - The device can be reset under program control.
Document Number: 001-55035 Rev. *G
Page 26 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
In normal operating mode, the program cannot disable the digital PRES circuit. The analog regulator can be disabled, which also disables the analog portion of the PRES. The PRES circuit is disabled automatically during sleep and hibernate modes, with one exception: During sleep mode the regulators are periodically activated (buzzed) to provide supervisory services and to reduce wakeup time. At these times the PRES circuit is also buzzed to allow periodic voltage monitoring.
ALVI, DLVI, AHVI - Analog/Digital Low Voltage Interrupt, Analog
6.3.1.2 Other Reset Sources
XRES - External Reset
CY8C53 has either a single GPIO pin that is configured as an external reset or a dedicated XRES pin. Either the dedicated XRES pin or the GPIO pin, if configured, holds the part in reset while held active (low). The response to an XRES is the same as to an IPOR reset. The external reset is active low. It includes an internal pull-up resistor. XRES is active during sleep and hibernate modes.
SRES - Software Reset
High Voltage Interrupt
Interrupt circuits are available to detect when VDDA and VDDD go outside a voltage range. For AHVI, VDDA is compared to a fixed trip level. For ALVI and DLVI, VDDA and VDDD are compared to trip levels that are programmable, as listed in Table 6-5. ALVI and DLVI can also be configured to generate a device reset instead of an interrupt. Table 6-5. Analog/Digital Low Voltage Interrupt, Analog High Voltage Interrupt Interrupt Supply DLVI VDDD VDDA VDDA Normal Voltage Range Available Trip Accuracy Settings 2%
A reset can be commanded under program control by setting a bit in the software reset register. This is done either directly by the program or indirectly by DMA access. The response to a SRES is the same as after an IPOR reset. Another register bit exists to disable this function.
DRES - Digital Logic Reset
1.71 V-5.5 V 1.70 V-5.45 V in 250 mV increments 1.71 V-5.5 V 1.70 V-5.45 V in 250 mV increments 1.71 V-5.5 V 5.75 V
A logic signal can be routed from the UDBs or other digital peripheral source through the DSI to the Configurable XRES pin, P1[2], to generate a hardware-controlled reset. The pin must be placed in XRES mode. The response to a DRES is the same as after an IPOR reset.
WRES - Watchdog Timer Reset
ALVI
2%
AHVI
2%
The watchdog reset detects when the software program is no longer being executed correctly. To indicate to the watchdog timer that it is running correctly, the program must periodically reset the timer. If the timer is not reset before a user-specified amount of time, then a reset is generated. Note IPOR disables the watchdog function. The program must enable the watchdog function at an appropriate point in the code by setting a register bit. When this bit is set, it cannot be cleared again except by an IPOR power on reset event.
The monitors are disabled until after IPOR. During sleep mode these circuits are periodically activated (buzzed). If an interrupt occurs during buzzing then the system first enters its wakeup sequence. The interrupt is then recognized and may be serviced.
Document Number: 001-55035 Rev. *G
Page 27 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Access port control and configuration registers on either port basis or pin basis Separate port read (PS) and write (DR) data registers to avoid read modify write errors Special functionality on a pin by pin basis
6.4 I/O System and Routing
PSoC I/Os are extremely flexible. Every GPIO has analog and digital I/O capability. All I/Os have a large number of drive modes, which are set at POR. PSoC also provides up to four individual I/O voltage domains through the VDDIO pins. There are two types of I/O pins on every device; those with USB provide a third type. Both General Purpose I/O (GPIO) and Special I/O (SIO) provide similar digital functionality. The primary differences are their analog capability and drive strength. Devices that include USB also provide two USBIO pins that support specific USB functionality as well as limited GPIO capability. All I/O pins are available for use as digital inputs and outputs for both the CPU and digital peripherals. In addition, all I/O pins can generate an interrupt. The flexible and advanced capabilities of the PSoC I/O, combined with any signal to any pin routability, greatly simplify circuit design and board layout. All GPIO pins can be used for analog input, CapSense[6], and LCD segment drive, while SIO pins are used for voltages in excess of VDDA and for programmable output voltages.
Features supported by both GPIO and SIO:
Additional features only provided on the GPIO pins:
LCD segment drive on LCD equipped devices CapSense on CapSense equipped devices[6] Analog input and output capability Continuous 100 A clamp current capability Standard drive strength down to 1.71 V

Additional features only provided on SIO pins:
Higher drive strength than GPIO Hot swap capability (5 V tolerance at any operating VDD) Programmable and regulated high input and output drive levels down to 1.2 V No analog input or LCD capability Over voltage tolerance up to 5.5 V SIO can act as a general purpose analog comparator

USBIO features:
User programmable port reset state Separate I/O supplies and voltages for up to four groups of I/O Digital peripherals use DSI to connect the pins Input or output or both for CPU and DMA Eight drive modes Every pin can be an interrupt source configured as rising edge, falling edge or both edges. If required, level sensitive interrupts are supported through the DSI Dedicated port interrupt vector for each port Slew rate controlled digital output drive mode
Full speed USB 2.0 compliant I/O Highest drive strength for general purpose use Input, output, or both for CPU and DMA Input, output, or both for digital peripherals Digital output (CMOS) drive mode Each pin can be an interrupt source configured as rising edge, falling edge, or both edges

Document Number: 001-55035 Rev. *G
Page 28 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Figure 6-8. GPIO Block Diagram
Digital Input Path
PRT[x]CTL PRT[x]DBL_SYNC_IN PRT[x]PS Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Pin Interrupt Signal PICU[x]INTSTAT Input Buffer Disable Interrupt Logic
Naming Convention `x' = Port Number `y' = Pin Number
Digital Output Path
PRT[x]SLW PRT[x]SYNC_OUT PRT[x]DR Digital System Output PRT[x]BYP PRT[x]DM2 PRT[x]DM1 PRT[x]DM0 Bidirectional Control PRT[x]BIE Drive Logic Slew Cntl
0 1
Vddio Vddio In Vddio
PIN
OE
Analog
1
0 1 0 1
Capsense Global Control CAPS[x]CFG1 PRT[x]AG Analog Global Enable PRT[x]AMUX Analog Mux Enable
Switches
LCD
PRT[x]LCD_COM_SEG PRT[x]LCD_EN LCD Bias Bus 5 Display Data Logic & MUX
Document Number: 001-55035 Rev. *G
Page 29 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Figure 6-9. SIO Input/Output Block Diagram
Digital Input Path
PRT[x]SIO_HYST_EN PRT[x]SIO_DIFF Reference Level PRT[x]DBL_SYNC_IN PRT[x]PS Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Pin Interrupt Signal PICU[x]INTSTAT Input Buffer Disable Interrupt Logic Buffer Thresholds Naming Convention `x' = Port Number `y' = Pin Number
Digital Output Path
Reference Level PRT[x]SIO_CFG PRT[x]SLW PRT[x]SYNC_OUT PRT[x]DR Digital System Output PRT[x]BYP PRT[x]DM2 PRT[x]DM1 PRT[x]DM0 Bidirectional Control PRT[x]BIE Drive Logic Slew Cntl
0 1
Driver Vhigh
In
PIN
OE
Figure 6-10. USBIO Block Diagram
Digital Input Path
USB Receiver Circuitry PRT[x]DBL_SYNC_IN USBIO_CR1[0,1] Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Pin Interrupt Signal PICU[x]INTSTAT Interrupt Logic Naming Convention `x' = Port Number `y' = Pin Number
Digital Output Path
PRT[x]SYNC_OUT USBIO_CR1[7] USB SIE Control for USB Mode USBIO_CR1[4,5] Digital System Output PRT[x]BYP USBIO_CR1[2] USBIO_CR1[3] USBIO_CR1[6]
0 1
D+ pin only USB or I/O
Vddd Vddd Vddd Vddd
In
Drive Logic
5k
1.5 k
PIN
D+ 1.5 k D+D- 5 k Open Drain
Document Number: 001-55035 Rev. *G
Page 30 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
6.4.1 Drive Modes Each GPIO and SIO pin is individually configurable into one of the eight drive modes listed in Table 6-6. Three configuration bits are used for each pin (DM[2:0]) and set in the PRTxDM[2:0] registers. Figure 6-11 depicts a simplified pin view based on each of the eight drive modes. Table 6-6 shows the I/O pin's drive state based on the port data register value or digital array signal
if bypass mode is selected. Note that the actual I/O pin voltage is determined by a combination of the selected drive mode and the load at the pin. For example, if a GPIO pin is configured for resistive pull-up mode and driven high while the pin is floating, the voltage measured at the pin is a high logic state. If the same GPIO pin is externally tied to ground then the voltage unmeasured at the pin is a low logic state.
Figure 6-11. Drive Mode
Vddio Vddio
DR PS
Pin
DR PS
Pin
DR PS
Pin
DR PS
Pin
0.
High Impedance Analog
1. High Impedance Digital
Vddio
2. Resistive Pull-Up
Vddio
3. Resistive Pull-Down
Vddio
DR PS
Pin
DR PS
Pin
DR PS
Pin
DR PS
Pin
4. Open Drain , Drives Low
5. Open Drain , Drives High
6. Strong Drive
7. Resistive Pull-Up and Pull-Down
Table 6-6. Drive Modes Diagram 0 1 2 3 4 5 6 7 Drive Mode High impedence analog High Impedance digital Resistive pull-up[8] Resistive pull-down[8] Open drain, drives low Open drain, drive high Strong drive Resistive pull-up and pull-down[8] PRTxDM2 0 0 0 0 1 1 1 1 PRTxDM1 0 0 1 1 0 0 1 1 PRTxDM0 0 1 0 1 0 1 0 1 PRTxDR = 1 High-Z High-Z Res High (5K) Strong High High-Z Strong High Strong High Res High (5K) PRTxDR = 0 High-Z High-Z Strong Low Res Low (5K) Strong Low High-Z Strong Low Res Low (5K)
High Impedance Analog
The default reset state with both the output driver and digital input buffer turned off. This prevents any current from flowing in the I/O's digital input buffer due to a floating voltage. This state is recommended for pins that are floating or that support an analog voltage. High impedance analog pins do not provide digital input functionality.
To achieve the lowest chip current in sleep modes, all I/Os must either be configured to the high impedance analog mode, or have their pins driven to a power supply rail by the PSoC device or by external circuitry.
High Impedance Digital
The input buffer is enabled for digital signal input. This is the standard high impedance (HiZ) state recommended for digital inputs.
Note 8. Resistive pull-up and pull-down are not available with SIO in regulated output mode. Document Number: 001-55035 Rev. *G Page 31 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Resistive pull-up or resistive pull-down
6.4.5 Pin Interrupts All GPIO and SIO pins are able to generate interrupts to the system. All eight pins in each port interface to their own Port Interrupt Control Unit (PICU) and associated interrupt vector. Each pin of the port is independently configurable to detect rising edge, falling edge, both edge interrupts, or to not generate an interrupt. Depending on the configured mode for each pin, each time an interrupt event occurs on a pin, its corresponding status bit of the interrupt status register is set to "1" and an interrupt request is sent to the interrupt controller. Each PICU has its own interrupt vector in the interrupt controller and the pin status register providing easy determination of the interrupt source down to the pin level. Port pin interrupts remain active in all sleep modes allowing the PSoC device to wake from an externally generated interrupt. While level sensitive interrupts are not directly supported; Universal Digital Blocks (UDB) provide this functionality to the system when needed. 6.4.6 Input Buffer Mode GPIO and SIO input buffers can be configured at the port level for the default CMOS input thresholds or the optional LVTTL input thresholds. All input buffers incorporate Schmitt triggers for input hysteresis. Additionally, individual pin input buffers can be disabled in any drive mode. 6.4.7 I/O Power Supplies Up to four I/O pin power supplies are provided depending on the device and package. Each I/O supply must be less than or equal to the voltage on the chip's analog (VDDA) pin. This feature allows users to provide different I/O voltage levels for different pins on the device. Refer to the specific device package pinout to determine VDDIO capability for a given port and pin. The SIO port pins support an additional regulated high output capability, as described in Adjustable Output Level. 6.4.8 Analog Connections These connections apply only to GPIO pins. All GPIO pins may be used as analog inputs or outputs. The analog voltage present on the pin must not exceed the VDDIO supply voltage to which the GPIO belongs. Each GPIO may connect to one of the analog global busses or to one of the analog mux buses to connect any pin to any internal analog resource such as ADC or comparators. In addition, select pins provide direct connections to specific analog features such as the high current DACs or uncommitted opamps. 6.4.9 CapSense This section applies only to GPIO pins. All GPIO pins may be used to create CapSense buttons and sliders[6]. See the "CapSense" section on page 54 for more information. 6.4.10 LCD Segment Drive This section applies only to GPIO pins. All GPIO pins may be used to generate Segment and Common drive signals for direct glass drive of LCD glass. See the "LCD Direct Drive" section on page 53 for details.
Resistive pull-up or pull-down, respectively, provides a series resistance in one of the data states and strong drive in the other. Pins can be used for digital input and output in these modes. Interfacing to mechanical switches is a common application for these modes. Resistive pull-up and pull-down are not available with SIO in regulated output mode.
Open drain, drives high and open drain, drives low
Open drain modes provide high impedance in one of the data states and strong drive in the other. Pins can be used for digital input and output in these modes. A common application for these modes is driving the I2C bus signal lines.
Strong drive
Provides a strong CMOS output drive in either high or low state. This is the standard output mode for pins. Strong Drive mode pins must not be used as inputs under normal circumstances. This mode is often used to drive digital output signals or external FETs.
Resistive pull-up and pull-down
Similar to the resistive pull-up and resistive pull-down modes except the pin is always in series with a resistor. The high data state is pull-up while the low data state is pull-down. This mode is most often used when other signals that may cause shorts can drive the bus. Resistive pull-up and pull-down are not available with SIO in regulated output mode. 6.4.2 Pin Registers Registers to configure and interact with pins come in two forms that may be used interchangeably. All I/O registers are available in the standard port form, where each bit of the register corresponds to one of the port pins. This register form is efficient for quickly reconfiguring multiple port pins at the same time. I/O registers are also available in pin form, which combines the eight most commonly used port register bits into a single register for each pin. This enables very fast configuration changes to individual pins with a single register write. 6.4.3 Bidirectional Mode High speed bidirectional capability allows pins to provide both the high impedance digital drive mode for input signals and a second user selected drive mode such as strong drive (set using PRTxDM[2:0] registers) for output signals on the same pin, based on the state of an auxiliary control bus signal. The bidirectional capability is useful for processor busses and communications interfaces such as the SPI Slave MISO pin that requires dynamic hardware control of the output buffer. The auxiliary control bus routes up to 16 UDB or digital peripheral generated output enable signals to one or more pins. 6.4.4 Slew Rate Limited Mode GPIO and SIO pins have fast and slow output slew rate options for strong and open drain drive modes, not resistive drive modes. Because it results in reduced EMI, the slow edge rate option is recommended for signals that are not speed critical, generally less than 1 MHz. The fast slew rate is for signals between 1 MHz and 33 MHz. The slew rate is individually configurable for each pin, and is set by the PRTxSLW registers.
Document Number: 001-55035 Rev. *G
Page 32 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
6.4.11 Adjustable Output Level This section applies only to SIO pins. SIO port pins support the ability to provide a regulated high output level for interface to external signals that are lower in voltage than the SIO's respective VDDIO. SIO pins are individually configurable to output either the standard VDDIO level or the regulated output, which is based on an internally generated reference. Typically a voltage DAC (VDAC) is used to generate the reference. The "DAC" section on page 54 has more details on VDAC use and reference routing to the SIO pins. Resistive pull-up and pull-down drive modes are not available with SIO in regulated output mode. 6.4.12 Adjustable Input Level This section applies only to SIO pins. SIO pins by default support the standard CMOS and LVTTL input levels but also support a differential mode with programmable levels. SIO pins are grouped into pairs. Each pair shares a reference generator block which, is used to set the digital input buffer reference level for interface to external signals that differ in voltage from VDDIO. The reference sets the pins voltage threshold for a high logic level. Available input thresholds are:
0.5 xVDDIO 0.4 xVDDIO 0.5 xVREF VREF
The GPIO pins must be limited to 100 A using a current limiting
resistor. GPIO pins clamp the pin voltage to approximately one diode above the VDDIO supply. analog voltage on the pin must not exceed the VDDIO supply voltage to which the GPIO belongs.
In case of a GPIO pin configured for analog input/output, the
A common application for this feature is connection to a bus such as I2C where different devices are running from different supply voltages. In the I2C case, the PSoC chip is configured into the Open Drain, Drives Low mode for the SIO pin. This allows an external pull-up to pull the I2C bus voltage above the PSoC pin supply. For example, the PSoC chip could operate at 1.8 V, and an external device could run from 5 V. Note that the SIO pin's VIH and VIL levels are determined by the associated VDDIO supply pin. The I/O pin must be configured into a high impedance drive mode, open drain low drive mode, or pull-down drive mode, for over voltage tolerance to work properly. Absolute maximum ratings for the device must be observed for all I/O pins. 6.4.16 Reset Configuration While reset is active all I/Os are reset to and held in the High Impedance Analog state. After reset is released, the state can be reprogrammed on a port-by-port basis to pull-down or pull-up. To ensure correct reset operation, the port reset configuration data is stored in special nonvolatile registers. The stored reset data is automatically transferred to the port reset configuration registers at reset release. 6.4.17 Low Power Functionality In all low power modes the I/O pins retain their state until the part is awakened and changed or reset. To awaken the part, use a pin interrupt, because the port interrupt logic continues to function in all low power modes. 6.4.18 Special Pin Functionality Some pins on the device include additional special functionality in addition to their GPIO or SIO functionality. The specific special function pins are listed in "Pinouts" on page 5. The special features are:
Digital
Typically a voltage DAC (VDAC) generates the VREF reference. "DAC" section on page 54 has more details on VDAC use and reference routing to the SIO pins. 6.4.13 SIO as Comparator This section applies only to SIO pins. The adjustable input level feature of the SIOs as explained in the Adjustable Input Level section can be used to construct a comparator. The threshold for the comparator is provided by the SIO's reference generator. The reference generator has the option to set the analog signal routed through the analog global line as threshold for the comparator. Note that a pair of SIO pins share the same threshold. The digital input path in Figure 6-9 on page 30 illustrates this functionality. In the figure, `Reference level' is the analog signal routed through the analog global. The hysteresis feature can also be enabled for the input buffer of the SIO, which increases noise immunity for the comparator. 6.4.14 Hot Swap This section applies only to SIO pins. SIO pins support `hot swap' capability to plug into an application without loading the signals that are connected to the SIO pins even when no power is applied to the PSoC device. This allows the unpowered PSoC to maintain a high impedance load to the external device while also preventing the PSoC from being powered through a GPIO pin's protection diode. 6.4.15 Over Voltage Tolerance All I/O pins provide an over voltage (VDDIO < VIN < VDDA) tolerance feature at any operating VDD.
There are no current limitations for the SIO pins as they present
4- to 33-MHz crystal oscillator 32.768-kHz crystal oscillator 2 Wake from sleep on I C address match. Any pin can be used 2C if wake from sleep is not required. for I JTAG interface pins SWD interface pins SWV interface pins External reset

Analog
Opamp inputs and outputs High current IDAC outputs External reference inputs

6.4.19 JTAG Boundary Scan The device supports standard JTAG boundary scan chains on all pins for board level test.
a high impedance load to the external circuit.
Document Number: 001-55035 Rev. *G
Page 33 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
7. Digital Subsystem
The digital programmable system creates application specific combinations of both standard and advanced digital peripherals and custom logic functions. These peripherals and logic are then interconnected to each other and to any pin on the device, providing a high level of design flexibility and IP security. The features of the digital programmable system are outlined here to provide an overview of capabilities and architecture. Designers do not need to interact directly with the programmable digital system at the hardware and register level. PSoC Creator provides a high level schematic capture graphical interface to automatically place and route resources similar to PLDs. The main components of the digital programmable system are:
Universal Digital Blocks (UDB) - These form the core
Figure 7-1. CY8C53 Digital Programmable Architecture
Digital Core System and Fixed Function Peripherals IO Port IO Port UDB Array
Page 34 of 102
DSI Routing Interface
UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB
UDB Array
UDB UDB UDB UDB
Universal Digital Block Array - UDB blocks are arrayed within
IO Port
a matrix of programmable interconnect. The UDB array structure is homogeneous and allows for flexible mapping of digital functions onto the array. The array supports extensive and flexible routing interconnects between UDBs and the Digital System Interconnect.
Digital Core System and Fixed Function Peripherals
Digital System Interconnect (DSI) - Digital signals from UDBs,
7.1 Example Peripherals
The flexibility of the CY8C53 family's UDBs and analog blocks allow the user to create a wide range of components (peripherals). The most common peripherals were built and characterized by Cypress and are shown in the PSoC Creator component catalog, however, users may also create their own custom components using PSoC Creator. Using PSoC Creator, users may also create their own components for reuse within their organization, for example sensor interfaces, proprietary algorithms, and display interfaces. The number of components available through PSoC Creator is too numerous to list in the datasheet, and the list is always growing. An example of a component available for use in CY8C53 family, but, not explicitly called out in this datasheet is the UART component.
fixed function peripherals, I/O pins, interrupts, DMA, and other system core signals are attached to the Digital System Interconnect to implement full featured device connectivity. The DSI allows any digital function to any pin or other feature routability when used with the Universal Digital Block Array.
Document Number: 001-55035 Rev. *G
IO Port
functionality of the digital programmable system. UDBs are a collection of uncommitted logic (PLD) and structural logic (Datapath) optimized to create all common embedded peripherals and customized functionality that are application or design specific.
DSI Routing Interface
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
7.1.1 Example Digital Components The following is a sample of the digital components available in PSoC Creator for the CY8C53 family. The exact amount of hardware resources (UDBs, routing, RAM, flash) used by a component varies with the features selected in PSoC Creator for the component.
Communications
7.1.3 Example System Function Components The following is a sample of the system function components available in PSoC Creator for the CY8C53 family. The exact amount of hardware resources (UDBs, SC/CT blocks, routing, RAM, flash) used by a component varies with the features selected in PSoC Creator for the component.
CapSense LCD Drive LCD Control Filters
I2C (1 to 3 UDBs) UART (1 to 3 UDBs)
Functions
EMIF (External Memory Interface, 1 UDB)
Logic (x CPLD product terms per logic function)
7.1.4 Designing with PSoC Creator 7.1.4.1 More Than a Typical IDE A successful design tool allows for the rapid development and deployment of both simple and complex designs. It reduces or eliminates any learning curve. It makes the integration of a new design into the production stream straightforward. PSoC Creator is that design tool. PSoC Creator is a full featured Integrated Development Environment (IDE) for hardware and software design. It is optimized specifically for PSoC devices and combines a modern, powerful software development platform with a sophisticated graphical design tool. This unique combination of tools makes PSoC Creator the most flexible embedded design platform available. Graphical design entry simplifies the task of configuring a particular part. You can select the required functionality from an extensive catalog of components and place it in your design. All components are parameterized and have an editor dialog that allows you to tailor functionality to your needs.
NOT OR XOR AND
7.1.2 Example Analog Components The following is a sample of the analog components available in PSoC Creator for the CY8C53 family. The exact amount of hardware resources (SC/CT blocks, routing, RAM, flash) used by a component varies with the features selected in PSoC Creator for the component.
Amplifiers
TIA PGA opamp

ADC
Successive Approximation (SAR)
DACs
Current Voltage PWM

Comparators Mixers
Document Number: 001-55035 Rev. *G
Page 35 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
PSoC Creator automatically configures clocks and routes the I/O to the selected pins and then generates APIs to give the application complete control over the hardware. Changing the PSoC device configuration is as simple as adding a new component, setting its parameters, and rebuilding the project. At any stage of development you are free to change the hardware configuration and even the target processor. To retarget your application (hardware and software) to new
devices, even from 8- to 32-bit families, just select the new device and rebuild. You also have the ability to change the C compiler and evaluate an alternative. Components are designed for portability and are validated against all devices, from all families, and against all supported tool chains. Switching compilers is as easy as editing the from the project options and rebuilding the application with no errors from the generated APIs or boot code.
Figure 7-2. PSoC Creator Framework
Document Number: 001-55035 Rev. *G
Page 36 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
7.1.4.2 Component Catalog Figure 7-3. Component Catalog
7.1.4.4 Software Development Figure 7-4. Code Editor
Anchoring the tool is a modern, highly customizable user interface. It includes project management and integrated editors for C and assembler source code, as well the design entry tools. Project build control leverages compiler technology from top commercial vendors such as ARM(R) Limited, KeilTM, and CodeSourcery (GNU). Free versions of Keil C51 and GNU C Compiler (GCC) for ARM, with no restrictions on code size or end product distribution, are included with the tool distribution. Upgrading to more optimizing compilers is a snap with support for the professional Keil C51 product and ARM RealViewTM compiler. 7.1.4.5 Nonintrusive Debugging Figure 7-5. PSoC Creator Debugger
The component catalog is a repository of reusable design elements that select device functionality and customize your PSoC device. It is populated with an impressive selection of content; from simple primitives such as logic gates and device registers, through the digital timers, counters and PWMs, plus analog components such as ADC, DACs, and filters, and communication protocols, such as I2C, USB and CAN. See "Example Peripherals" section on page 34 for more details about available peripherals. All content is fully characterized and carefully documented in datasheets with code examples, AC/DC specifications, and user code ready APIs. 7.1.4.3 Design Reuse The symbol editor gives you the ability to develop reusable components that can significantly reduce future design time. Just draw a symbol and associate that symbol with your proven design. PSoC Creator allows for the placement of the new symbol anywhere in the component catalog along with the content provided by Cypress. You can then reuse your content as many times as you want, and in any number of projects, without ever having to revisit the details of the implementation.
With JTAG (4-wire) and SWD (2-wire) debug connectivity available on all devices, the PSoC Creator debugger offers full control over the target device with minimum intrusion. Breakpoints and code execution commands are all readily available from toolbar buttons and an impressive lineup of windows--register, locals, watch, call stack, memory and peripherals--make for an unparalleled level of visibility into the system.
Document Number: 001-55035 Rev. *G Page 37 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
of compare configurations and condition generation. This block also contains input/output FIFOs, which are the primary parallel data interface between the CPU/DMA system and the UDB.
PSoC Creator contains all the tools necessary to complete a design, and then to maintain and extend that design for years to come. All steps of the design flow are carefully integrated and optimized for ease-of-use and to maximize productivity.
Status and Control Module - The primary role of this block is to
7.2 Universal Digital Block
The Universal Digital Block (UDB) represents an evolutionary step to the next generation of PSoC embedded digital peripheral functionality. The architecture in first generation PSoC digital blocks provides coarse programmability in which a few fixed functions with a small number of options are available. The new UDB architecture is the optimal balance between configuration granularity and efficient implementation. A cornerstone of this approach is to provide the ability to customize the devices digital operation to match application requirements. To achieve this, UDBs consist of a combination of uncommitted logic (PLD), structured logic (Datapath), and a flexible routing scheme to provide interconnect between these elements, I/O connections, and other peripherals. UDB functionality ranges from simple self contained functions that are implemented in one UDB, or even a portion of a UDB (unused resources are available for other functions), to more complex functions that require multiple UDBs. Examples of basic functions are timers, counters, CRC generators, PWMs, dead band generators, and communications functions, such as UARTs, SPI, and I2C. Also, the PLD blocks and connectivity provide full featured general purpose programmable logic within the limits of the available resources. Figure 7-6. UDB Block Diagram
provide a way for CPU firmware to interact and synchronize with UDB operation. and reset selection and control.
Clock and Reset Module - This block provides the UDB clocks
7.2.1 PLD Module The primary purpose of the PLD blocks is to implement logic expressions, state machines, sequencers, look up tables, and decoders. In the simplest use model, consider the PLD blocks as a standalone resource onto which general purpose RTL is synthesized and mapped. The more common and efficient use model is to create digital functions from a combination of PLD and datapath blocks, where the PLD implements only the random logic and state portion of the function while the datapath (ALU) implements the more structured elements. Figure 7-7. PLD 12C4 Structure
PT0 PT1 PT2 PT3 PT4 PT5 PT6 TC TC TC TC TC TC TC TC TC TC TC TC IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 IN10 TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC AND Array PT7 T T T T
PLD Chaining Clock and Reset Control PLD 12C4 (8 PTs) PLD 12C4 (8 PTs)
OUT0 OUT1
IN11 SELIN (carry in)
MC0 MC1 MC2 MC3
T T T T
T T T T
T T T T
T T T T
T T T T
T T T T
T T T T
Status and Control
OUT2
Datapath
Datapath Chaining
OUT3
SELOUT (carry out)
OR Array
Routing Channel
The main component blocks of the UDB are:
PLD blocks - There are two small PLDs per UDB. These blocks
take inputs from the routing array and form registered or combinational sum-of-products logic. PLDs are used to implement state machines, state bits, and combinational logic equations. PLD configuration is automatically generated from graphical primitives. logic to implement a dynamically configurable ALU, a variety
Datapath Module - This 8-bit wide datapath contains structured
One 12C4 PLD block is shown in Figure 7-7. This PLD has 12 inputs, which feed across eight product terms. Each product term (AND function) can be from 1 to 12 inputs wide, and in a given product term, the true (T) or complement (C) of each input can be selected. The product terms are summed (OR function) to create the PLD outputs. A sum can be from 1 to 8 product terms wide. The 'C' in 12C4 indicates that the width of the OR gate (in this case 8) is constant across all outputs (rather than variable as in a 22V 10 device). This PLA like structure gives maximum flexibility and insures that all inputs and outputs are permutable for ease of allocation by the software tools. There are two 12C4 PLDs in each UDB.
Document Number: 001-55035 Rev. *G
Page 38 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
7.2.2 Datapath Module The datapath contains an 8-bit single cycle ALU, with associated compare and condition generation logic. This datapath block is optimized to implement embedded functions, such as timers, counters, integrators, PWMs, PRS, CRC, shifters and dead band generators and many others. Figure 7-8. Datapath Top Level
PHUB System Bus R/W Access to All Registers F1 FIFOs Datapath Control Control Store RAM 8 Word X 16 Bit Input from Programmable Routing Input Muxes 6 F0 A0 A1 D0 D1 Conditions: 2 Compares, 2 Zero Detect, 2 Ones Detect Overflow Detect Output Muxes 6 Output to Programmable Routing
D1 Data Registers D0
A1 Accumulators A0 PI Parallel Input/Output (To/From Programmable Routing) PO
To/From Previous Datapath
Chaining
To/From Next Datapath
ALU Shift Mask
7.2.2.6 Working Registers The datapath contains six primary working registers, which are accessed by CPU firmware or DMA during normal operation. Table 7-1. Working Datapath Registers Name Function Description These are sources and sinks for the ALU and also sources for the compares. These are sources for the ALU and sources for the compares. These are the primary interface to the system bus. They can be a data source for the data registers and accumulators or they can capture data from the accumulators or ALU. Each FIFO is four bytes deep. A0 and A1 Accumulators
7.2.2.7 Dynamic Datapath Configuration RAM Dynamic configuration is the ability to change the datapath function and internal configuration on a cycle-by-cycle basis, under sequencer control. This is implemented using the 8-word x 16-bit configuration RAM, which stores eight unique 16-bit wide configurations. The address input to this RAM controls the sequence, and can be routed from any block connected to the UDB routing matrix, most typically PLD logic, I/O pins, or from the outputs of this or other datapath blocks. ALU The ALU performs eight general purpose functions. They are:
Increment Decrement Add Subtract Logical AND
D0 and D1 Data Registers F0 and F1 FIFOs
Document Number: 001-55035 Rev. *G
Page 39 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Logical OR Logical XOR Pass, used to pass a value through the ALU to the shift register,
Figure 7-9. Example FIFO Configurations
System Bus System Bus
mask, or another UDB register
Independent of the ALU operation, these functions are available:
Shift left Shift right Nibble swap Bitwise OR mask
F0
F0
F1
D0/D1 A0/A1/ALU
A0/A1/ALU
A0/A1/ALU
D0 A0
D1 A1
F1
F0
F1
7.2.2.8 Conditionals Each datapath has two compares, with bit masking options. Compare operands include the two accumulators and the two data registers in a variety of configurations. Other conditions include zero detect, all ones detect, and overflow. These conditions are the primary datapath outputs, a selection of which can be driven out to the UDB routing matrix. Conditional computation can use the built in chaining to neighboring UDBs to operate on wider data widths without the need to use routing resources. 7.2.2.9 Variable MSB The most significant bit of an arithmetic and shift function can be programmatically specified. This supports variable width CRC and PRS functions, and in conjunction with ALU output masking, can implement arbitrary width timers, counters and shift blocks. 7.2.2.10 Built in CRC/PRS The datapath has built in support for single cycle Cyclic Redundancy Check (CRC) computation and Pseudo Random Sequence (PRS) generation of arbitrary width and arbitrary polynomial. CRC/PRS functions longer than 8 bits may be implemented in conjunction with PLD logic, or built in chaining may be use to extend the function into neighboring UDBs. 7.2.2.11 Input/Output FIFOs Each datapath contains two four-byte deep FIFOs, which can be independently configured as an input buffer (system bus writes to the FIFO, datapath internal reads the FIFO), or an output buffer (datapath internal writes to the FIFO, the system bus reads from the FIFO). The FIFOs generate status that are selectable as datapath outputs and can therefore be driven to the routing, to interact with sequencers, interrupts, or DMA.
System Bus TX/RX System Bus Dual Capture Dual Buffer
7.2.2.12 Chaining The datapath can be configured to chain conditions and signals such as carries and shift data with neighboring datapaths to create higher precision arithmetic, shift, CRC/PRS functions. 7.2.2.13 Time Multiplexing In applications that are over sampled, or do not need high clock rates, the single ALU block in the datapath can be efficiently shared with two sets of registers and condition generators. Carry and shift out data from the ALU are registered and can be selected as inputs in subsequent cycles. This provides support for 16-bit functions in one (8-bit) datapath. 7.2.2.14 Datapath I/O There are six inputs and six outputs that connect the datapath to the routing matrix. Inputs from the routing provide the configuration for the datapath operation to perform in each cycle, and the serial data inputs. Inputs can be routed from other UDB blocks, other device peripherals, device I/O pins, and so on. The outputs to the routing can be selected from the generated conditions, and the serial data outputs. Outputs can be routed to other UDB blocks, device peripherals, interrupt and DMA controller, I/O pins, and so on. 7.2.3 Status and Control Module The primary purpose of this circuitry is to coordinate CPU firmware interaction with internal UDB operation.
Document Number: 001-55035 Rev. *G
Page 40 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Figure 7-10. Status and Control Registers
System Bus
are highly permutable providing efficient automatic routing in PSoC Creator. Additionally the routing allows wire by wire segmentation along the vertical and horizontal routing to further increase routing flexibility and capability. Figure 7-11. Digital System Interface Structure
8-bit Status Register (Read Only)
8-bit Control Register (Write/Read)
HV B
System Connections
HV A
HV B
HV A
Routing Channel
UDB
UDB
UDB
UDB
The bits of the control register, which may be written to by the system bus, are used to drive into the routing matrix, and thus provide firmware with the opportunity to control the state of UDB processing. The status register is read-only and it allows internal UDB state to be read out onto the system bus directly from internal routing. This allows firmware to monitor the state of UDB processing. Each bit of these registers has programmable connections to the routing matrix and routing connections are made depending on the requirements of the application. 7.2.3.15 Usage Examples As an example of control input, a bit in the control register can be allocated as a function enable bit. There are multiple ways to enable a function. In one method the control bit output would be routed to the clock control block in one or more UDBs and serve as a clock enable for the selected UDB blocks. A status example is a case where a PLD or datapath block generated a condition, such as a "compare true" condition that is captured and latched by the status register and then read (and cleared) by CPU firmware. 7.2.3.16 Clock Generation Each subcomponent block of a UDB including the two PLDs, the datapath, and Status and Control, has a clock selection and control block. This promotes a fine granularity with respect to allocating clocking resources to UDB component blocks and allows unused UDB resources to be used by other functions for maximum system efficiency.
HV A
HV B
HV A
HV B
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
HV B
HV A
HV B
HV A
UDB
UDB
UDB
UDB
HV A
HV B
HV A
HV B
System Connections
7.3.1 UDB Array Programmable Resources Figure 7-12 shows an example of how functions are mapped into a bank of 16 UDBs. The primary programmable resources of the UDB are two PLDs, one datapath and one status/control register. These resources are allocated independently, because they have independently selectable clocks, and therefore unused blocks are allocated to other unrelated functions. An example of this is the 8-bit Timer in the upper left corner of the array. This function only requires one datapath in the UDB, and therefore the PLD resources may be allocated to another function. A function such as a Quadrature Decoder may require more PLD logic than one UDB can supply and in this case can utilize the unused PLD blocks in the 8-bit Timer UDB. Programmable resources in the UDB array are generally homogeneous so functions can be mapped to arbitrary boundaries in the array.
7.3 UDB Array Description
Figure 7-11 shows an example of a 16 UDB array. In addition to the array core, there are a DSI routing interfaces at the top and bottom of the array. Other interfaces that are not explicitly shown include the system interfaces for bus and clock distribution. The UDB array includes multiple horizontal and vertical routing channels each comprised of 96 wires. The wire connections to UDBs, at horizontal/vertical intersection and at the DSI interface
Document Number: 001-55035 Rev. *G
Page 41 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Figure 7-12. Function Mapping Example in a Bank of UDBs
Sequencer 8-Bit Timer Quadrature Decoder UDB UDB 16-Bit PWM UDB 16-Bit PYRS UDB
Figure 7-13. Digital System Interconnect
Timer Counters Interrupt Controller DMA Controller IO Port Pins IO Port Pins
CAN
I2C
HV A
HV B
HV A
HV B
Digital System Routing I/F
UDB I2C Slave UDB
UDB 8-Bit SPI
UDB
UDB 8-Bit Timer Logic
12-Bit SPI UDB UDB UDB
UDB ARRAY
HV B
HV A Logic
HV B
HV A
Digital System Routing I/F
UDB UART
UDB
UDB 12-Bit PWM
UDB
Global Clocks Global Clocks SAR ADC SC Blocks
EMIF
DACS
Comparators
7.4 DSI Routing Interface Description
The DSI routing interface is a continuation of the horizontal and vertical routing channels at the top and bottom of the UDB array core. It provides general purpose programmable routing between device peripherals, including UDBs, I/Os, analog peripherals, interrupts, DMA and fixed function peripherals. Figure 7-13 illustrates the concept of the digital system interconnect, which connects the UDB array routing matrix with other device peripherals. Any digital core or fixed function peripheral that needs programmable routing is connected to this interface. Signals in this category include:
Interrupt requests from all digital peripherals in the system. DMA requests from all digital peripherals in the system. Digital peripheral data signals that need flexible routing to I/Os. Digital peripheral data signals that need connections to UDBs. Connections to the interrupt and DMA controllers. Connection to I/O pins. Connection to analog system digital signals.
Interrupt and DMA routing is very flexible in the CY8C53 programmable architecture. In addition to the numerous fixed function peripherals that can generate interrupt requests, any data signal in the UDB array routing can also be used to generate a request. A single peripheral may generate multiple independent interrupt requests simplifying system and firmware design. Figure 7-14 shows the structure of the IDMUX (Interrupt/DMA Multiplexer). Figure 7-14. Interrupt and DMA Processing in the IDMUX
Interrupt and DMA Processing in IDMUX Fixed Function IRQs
0 1 IRQs 2 Edge Detect DRQs DMA termout (IRQs) 0 1 Edge Detect 2 DMA Controller 3
Interrupt Controller
UDB Array
Fixed Function DRQs
Document Number: 001-55035 Rev. *G
Page 42 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
7.4.1 I/O Port Routing There are a total of 20 DSI routes to a typical 8-bit I/O port, 16 for data and four for drive strength control. When an I/O pin is connected to the routing, there are two primary connections available, an input and an output. In conjunction with drive strength control, this can implement a bidirectional I/O pin. A data output signal has the option to be single synchronized (pipelined) and a data input signal has the option to be double synchronized. The synchronization clock is the system clock (see Figure 6-1). Normally all inputs from pins are synchronized as this is required if the CPU interacts with the signal or any signal derived from it. Asynchronous inputs have rare uses. An example of this is a feed through of combinational PLD logic from input pins to output pins. Figure 7-15. I/O Pin Synchronization Routing
There are four more DSI connections to a given I/O port to implement dynamic output enable control of pins. This connectivity gives a range of options, from fully ganged 8-bits controlled by one signal, to up to four individually controlled pins. The output enable signal is useful for creating tri-state bidirectional pins and buses. Figure 7-17. I/O Pin Output Enable Connectivity
4 IO Control Signal Connections from UDB Array Digital System Interface
DO
OE PIN 0 OE PIN1 OE PIN2 OE PIN3 OE PIN4 OE PIN5 OE PIN6 OE PIN7
DI
Port i
Figure 7-16. I/O Pin Output Connectivity
8 IO Data Output Connections from the UDB Array Digital System Interface
7.5 CAN
The CAN peripheral is a fully functional Controller Area Network (CAN) supporting communication baud rates up to 1 Mbps. The CAN controller implements the CAN2.0A and CAN2.0B specifications as defined in the Bosch specification and conforms to the ISO-11898-1 standard. The CAN protocol was originally designed for automotive applications with a focus on a high level of fault detection. This ensures high communication reliability at a low cost. Because of its success in automotive applications, CAN is used as a standard communication protocol for motion oriented machine control networks (CANOpen) and factory automation applications (DeviceNet). The CAN controller features allow the efficient implementation of higher level protocols without affecting the performance of the microcontroller CPU. Full configuration support is provided in PSoC Creator.
DO PIN 0
DO PIN1
DO PIN2
DO PIN3
DO PIN4
DO PIN5
DO PIN6
DO PIN7
Port i
Document Number: 001-55035 Rev. *G
Page 43 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Figure 7-18. CAN Bus System Implementation
CAN Node 1 PSoC CAN Drivers CAN Controller
CAN Node 2
CAN Node n
En
Tx Rx
CAN Transceiver
CAN_H
CAN_L
CAN_H
CAN_L CAN Bus
CAN_H
CAN_L
7.5.1 CAN Features
CAN2.0A/B protocol implementation - ISO 11898 compliant
Receive path
Standard and extended frames with up to 8 bytes of data per frame Message filter capabilities Remote Transmission Request (RTR) support Programmable bit rate up to 1 Mbps
Listen Only mode SW readable error counter and indicator Sleep mode: Wake the device from sleep with activity on the
16 receive buffers each with its own message filter Enhanced hardware message filter implementation that covers the ID, IDE and RTR DeviceNet addressing support Multiple receive buffers linkable to build a larger receive message array Automatic transmission request (RTR) response handler Lost received message notification

Transmit path
Rx pin
Supports two or three wire interface to external transceiver (Tx,
Rx, and Enable). The three-wire interface is compatible with the Philips PHY; the PHY is not included on-chip. The three wires can be routed to any I/O CAN receive and transmit buffers status CAN controller error status including BusOff
Eight transmit buffers Programmable transmit priority * Round robin * Fixed priority Message transmissions abort capability

Enhanced interrupt controller
7.5.2 Software Tools Support CAN Controller configuration integrated into PSoC Creator:
CAN Configuration walkthrough with bit timing analyzer Receive filter setup
Document Number: 001-55035 Rev. *G
Page 44 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Figure 7-19. CAN Controller Block Diagram
TxMessage0 TxReq TxAbort
Tx Buffer Status TxReq Pending
TxMessage1 TxReq TxAbort Priority Arbiter
Bit Timing
TxInterrupt Request (if enabled)
TxMessage6 TxReq TxAbort
Tx CAN Framer
Tx CRC Generator
TxMessage7 TxReq TxAbort
RTR RxMessages 0-15
Error Status Error Active Error Passive Bus Off Tx Error Counter Rx Error Counter
Rx Buffer Status RxMessage Available
RxMessage0 RxMessage1
Acceptance Code 0 Acceptance Code 1
Acceptance Mask 0 Acceptance Mask 1 RxMessage Handler Rx CAN Framer CRC Check Rx
RxMessage14 RxInterrupt Request (if enabled) RxMessage15
Acceptance Code 14 Acceptance Code 15
Acceptance Mask 14 Acceptance Mask 15
ErrInterrupt Request (if enabled)
Error Detection CRC Form ACK Bit Stuffing Bit Error Overload Arbitration
WakeUp Request
7.6 USB
PSoC includes a dedicated Full-Speed (12 Mbps) USB 2.0 transceiver supporting all four USB transfer types: control, interrupt, bulk, and isochronous. The maximum data payload size is 64 bytes for control, interrupt, and bulk endpoints and 1023 bytes for isochronous. PSoC Creator provides full configuration support. USB interfaces to hosts through two dedicated USBIO pins, which are detailed in the "I/O System and Routing" section on page 28. USB includes the following features:
Eight unidirectional data endpoints One bidirectional control endpoint 0 (EP0) Shared 512-byte buffer for the eight data endpoints Dedicated 8-byte buffer for EP0 Three memory modes
Internal 48 MHz oscillator that auto locks to USB bus clock,
requiring no external crystal for USB (USB equipped parts only)
Interrupts on bus and each endpoint event, with device wakeup USB Reset, Suspend, and Resume operations Bus powered and self powered modes
Figure 7-20. USB
512 X 8 SRAM D+ SIE (Serial Interface Engine) Interrupts 48 MHz IMO USB I/O D- External 22 Resistors
Arbiter System Bus
Manual Memory Management with No DMA Access Manual Memory Management with Manual DMA Access Automatic Memory Management with Automatic DMA Access
Internal 3.3 V regulator for transceiver
Document Number: 001-55035 Rev. *G Page 45 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
7.7 Timers, Counters, and PWMs
The Timer/Counter/PWM peripheral is a 16-bit dedicated peripheral providing three of the most common embedded peripheral features. As almost all embedded systems use some combination of timers, counters, and PWMs. Four of them have been included on this PSoC device family. Additional and more advanced functionality timers, counters, and PWMs can also be instantiated in Universal Digital Blocks (UDBs) as required. PSoC Creator allows designers to choose the timer, counter, and PWM features that they require. The tool set utilizes the most optimal resources available. The Timer/Counter/PWM peripheral can select from multiple clock sources, with input and output signals connected through the DSI routing. DSI routing allows input and output connections to any device pin and any internal digital signal accessible through the DSI. Each of the four instances has a compare output, terminal count output (optional complementary compare output), and programmable interrupt request line. The Timer/Counter/PWMs are configurable as free running, one shot, or Enable input controlled. The peripheral has timer reset and capture inputs, and a kill input for control of the comparator outputs. The peripheral supports full 16-bit capture. Timer/Counter/PWM features include:
16-bit Timer/Counter/PWM (down count only) Selectable clock source PWM comparator (configurable for LT, LTE, EQ, GTE, GT) Period reload on start, reset, and terminal count Interrupt on terminal count, compare true, or capture Dynamic counter reads Timer capture mode Count while enable signal is asserted mode Free run mode One Shot mode (stop at end of period) Complementary PWM outputs with deadband PWM output kill
7.8 I2C
The I2C peripheral provides a synchronous two wire interface designed to interface the PSoC device with a two wire I2C serial communication bus. The bus is compliant with Philips `The I2C Specification' version 2.1. Additional I2C interfaces can be instantiated using Universal Digital Blocks (UDBs) in PSoC Creator, as required. To eliminate the need for excessive CPU intervention and overhead, I2C specific support is provided for status detection and generation of framing bits. I2C operates as a slave, a master, or multimaster (Slave and Master). In slave mode, the unit always listens for a start condition to begin sending or receiving data. Master mode supplies the ability to generate the Start and Stop conditions and initiate transactions. Multimaster mode provides clock synchronization and arbitration to allow multiple masters on the same bus. If Master mode is enabled and Slave mode is not enabled, the block does not generate interrupts on externally generated Start conditions. I2C interfaces through the DSI routing and allows direct connections to any GPIO or SIO pins. I2C provides hardware address detect of a 7-bit address without CPU intervention. Additionally the device can wake from low power modes on a 7-bit hardware address match. If wakeup functionality is required, I2C pin connections are limited to the two special sets of SIO pins. I2C features include:
Slave and Master, Transmitter, and Receiver operation Byte processing for low CPU overhead Interrupt or polling CPU interface Support for bus speeds up to 1 Mbps (3.4 Mbps in UDBs) 7 or 10-bit addressing (10-bit addressing requires firmware
support)
SMBus operation (through firmware support - SMBus
supported in hardware in UDBs)
7-bit hardware address compare Wake from low power modes on address match
Figure 7-21. Timer/Counter/PWM
Clock Reset Enable Capture Kill
Timer / Counter / PWM 16-bit
IRQ TC / Compare! Compare
Document Number: 001-55035 Rev. *G
Page 46 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
8. Analog Subsystem
The analog programmable system creates application specific combinations of both standard and advanced analog signal processing blocks. These blocks are then interconnected to each other and also to any pin on the device, providing a high level of design flexibility and IP security. The features of the analog subsystem are outlined here to provide an overview of capabilities and architecture.
Flexible, configurable analog routing architecture provided by
Four comparators with optional connection to configurable LUT
outputs
Two configurable switched capacitor/continuos time (SC/CT)
blocks for functions that include opamp, unity gain buffer, programmable gain amplifier, transimpedance amplifier, and mixer be used as high current output buffers
Two opamps for internal use and connection to GPIO that can CapSense subsystem to enable capacitive touch sensing Precision reference for generating an accurate analog voltage
analog globals, analog mux bus, and analog local buses
Successive approximation (SAR) ADC Two 8-bit DACs that provide either voltage or current output
for internal analog blocks
Figure 8-1. Analog Subsystem Block Diagram
SAR ADC
DAC
A N A L O G G P IO P o rt R O U T I N G
DAC
P re cisio n R e fe re n ce
A N A L O G R O U T I N G G P IO P o rt
S C /C T B lo c k Op Amp
S C /C T B lo c k
Op Amp
C o m p a ra to rs
CMP CMP CMP CMP
C a p S e n s e S u b s y s te m
A n a lo g In te rfa c e
C o n fig & S ta tu s R e g iste rs
PHUB
CPU
DSI A rra y
C lo c k D istrib u tio n
D e cim a to r
The PSoC Creator software program provides a user friendly interface to configure the analog connections between the GPIO and various analog resources and also connections from one analog resource to another. PSoC Creator also provides component libraries that allow you to configure the various
analog blocks to perform application specific functions (PGA, transimpedance amplifier, voltage DAC, current DAC, and so on). The tool also generates API interface libraries that allow you to write firmware that allows the communication between the analog peripheral and CPU/Memory.
Document Number: 001-55035 Rev. *G
Page 47 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
8.1 Analog Routing
The CY8C38 family of devices has a flexible analog routing architecture that provides the capability to connect GPIOs and different analog blocks, and also route signals between different analog blocks. One of the strong points of this flexible routing architecture is that it allows dynamic routing of input and output connections to the different analog blocks. 8.1.1 Features
Flexible, configurable analog routing architecture 16 Analog globals (AG) and two analog mux buses
8.1.2 Functional Description Analog globals (AGs) and analog mux buses (AMUXBUS) provide analog connectivity between GPIOs and the various analog blocks. There are 16 AGs in the CY8C38 family. The analog routing architecture is divided into four quadrants as shown in Figure 8-2. Each quadrant has four analog globals (AGL[0..3], AGL[4..7], AGR[0..3], AGR[4..7]). Each GPIO is connected to the corresponding AG through an analog switch. The analog mux bus is a shared routing resource that connects to every GPIO through an analog switch. There are two AMUXBUS routes in CY8C38, one in the left half (AMUXBUSL) and one in the right half (AMUXBUSR), as shown in Figure 8-2.
(AMUXBUS) to connect GPIOs and the analog blocks mux bus
Each GPIO is connected to one analog global and one analog 8 Analog local buses (abus) to route signals between the
different analog blocks analog blocks
Multiplexers and switches for input and output selection of the
Document Number: 001-55035 Rev. *G
Page 48 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Figure 8-2. CY8C53 Analog Interconnect
Vdda Vssa Vcca Vssd
swinn
swinp
AMUXBUSL AGL[4] AGL[5] AGL[6] AGL[7]
AMUXBUSR AGR[4] AGR[5] AGR[6] AGR[7] 44
*
*
AMUXBUSL
AGL[4] AGL[5]
AGL[6] AGL[7]
ExVrefL ExVrefL1
opamp0 swfol opamp2 swfol
ExVrefL2
GPIO P0[4] GPIO P0[5] GPIO P0[6] GPIO P0[7] GPIO P4[2] GPIO P4[3] GPIO P4[4] GPIO P4[5] GPIO P4[6] GPIO P4[7] Vccd Vssd
swinp
01 2 3 4 56 7 0123
3210 76543210
swinn
* *
i0 i2
abuf_vref_int (1.024V)
swout swin
in0 out0 + comp0
LPF
5
in1 out1 comp1 + swin
swout
cmp1_vref
cmp0_vref (1.024V) vref_cmp1 (0.256V) bg_vda_res_en Vdda Vdda/2
refbuf_vref1 (1.024V) refbuf_vref2 (1.2V) cmp_muxvn[1:0]
COMPARATOR
+ - comp2
bg_vda_swabusl0
cmp1_vref
refbufr_ cmp
refbufl_ cmp
90
comp3
+ -
cmp0_vref (1.024V)
cmp1_vref
AGR[7] AGR[6] AGR[5]
vssa
SC/CT
ABUSL0 ABUSL1 ABUSL2 ABUSL3 v0 DAC0 i0 v2 DAC2 i2
dac_vref (0.256V)
ABUSR0 ABUSR1 ABUSR2 ABUSR3
Vddd
AGL[1] AGL[2] AGL[3]
Vddio2
AMUXBUSL AGL[0]
:
TS ADC
VBE Vss ref
LPF
AGL[3] AGL[2] AGL[1] AGL[0] AMUXBUSL
AGR[3] AGR[2] AGR[1] AGR[0] AMUXBUSR
Connection
Vboost
Switch Resistance Small ( ~870 Ohms ) Large ( ~200 Ohms)
Notes: * Denotes pins on all packages LCD signals are not shown.
Vssb
Vssd
XRES
Vbat
Ind
Document Number: 001-55035 Rev. *G
Vddio1
GPIO P2[5] GPIO P2[6] GPIO P2[7] SIO P12[4] SIO P12[5] GPIO P6[4] GPIO P6[5] GPIO P6[6] GPIO P6[7]
GPIO P5[0] GPIO P5[1] GPIO P5[2] GPIO P5[3] GPIO P1[0] GPIO P1[1] GPIO P1[2] GPIO P1[3] GPIO P1[4] GPIO P1[5]
Mux Group Switch Group
*
*
*
*
*
*
*
*
13
AGR[0] AMUXBUSR
AGR[3] AGR[2] AGR[1]
GPIO P6[0] GPIO P6[1] GPIO P6[2] GPIO P6[3] GPIO P15[4] GPIO P15[5] GPIO P2[0] GPIO P2[1] GPIO P2[2] GPIO P2[3] * GPIO P2[4] *
VIDAC
36
SAR_vref1 (1.024V) SAR_vref2 (1.2V) Vdda Vdda/2
en_resvda
Vp (+) Vn (-) SAR0 Vrefhi_out refs
refmux[2:0]
CY8C55 only
SAR ADC
CY8C55 only
SAR_vref1 (1.024V) SAR_vref2 (1.2V) Vdda Vdda/2
en_resvda
ExVrefL1
ExVrefL2 ANALOG ANALOG BUS GLOBALS
refmux[2:0]
CY8C55 only
AMUXBUSL
01 23456 7 0123
ANALOG ANALOG GLOBALS BUS
3210 76543210
AMUXBUSR
Rev #51 2-April-2010
*
sc0_bgref (1.024V)
sc0 Vin Vref out
sc1 Vin Vref out
Vssa
sc1_bgref (1.024V)
AGR[4] AMUXBUSR
refsel[1:0]
out ref in refbufl
CAPSENSE
refbufr
out ref in
refbuf_vref1 (1.024V) refbuf_vref2 (1.2V)
refsel[1:0]
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Vddio0
Vddio3
GPIO P3[6] GPIO P3[7] SIO P12[0] SIO P12[1] GPIO P15[2] GPIO P15[3]
SIO P12[2] SIO P12[3] GPIO P4[0] GPIO P4[1] GPIO P0[0] GPIO P0[1] GPIO P0[2] GPIO P0[3]
*
ExVrefR
i3 i1
GPIO P3[5] GPIO P3[4] GPIO P3[3] GPIO P3[2] GPIO P3[1] GPIO P3[0] GPXT *P15[1] GPXT *P15[0]
* * * * * *
Vccd Vssd Vddd
* P15[7] * P15[6]
GPIO P5[7] GPIO P5[6] GPIO P5[5] GPIO P5[4] SIO P12[7] SIO P12[6] GPIO *P1[7] GPIO *P1[6]
USB IO USB IO
Page 49 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Analog local buses (abus) are routing resources located within the analog subsystem and are used to route signals between different analog blocks. There are eight abus routes in CY8C38, four in the left half (abusl [0:3]) and four in the right half (abusr [0:3]) as shown in Figure 8-2. Using the abus saves the analog globals and analog mux buses from being used for interconnecting the analog blocks. Multiplexers and switches exist on the various buses to direct signals into and out of the analog blocks. A multiplexer can have only one connection on at a time, whereas a switch can have multiple connections on simultaneously. In Figure 8-2, multiplexers are indicated by grayed ovals and switches are indicated by transparent ovals.
8.2.2 Conversion Signals Writing a start bit or assertion of a Start of Frame (SOF) signal is used to start a conversion. SOF can be used in applications where the sampling period is longer than the conversion time, or when the ADC needs to be synchronized to other hardware. This signal is optional and does not need to be connected if the SAR ADC is running in a continuous mode. A digital clock or UDB output can be used to drive this input. When the SAR is first powered up or awakened from any of the sleeping modes, there is a power up wait time of 10 s before it is ready to start the first conversion. When the conversion is complete, a status bit is set and the output signal End of Frame (EOF) asserts and remains asserted until the value is read by either the DMA controller or the CPU. The EOF signal may be used to trigger an interrupt or a DMA request. 8.2.3 Operational Modes A ONE_SHOT control bit is used to set the SAR ADC conversion mode to either continuous or one conversion per SOF signal. DMA transfer of continuous samples, without CPU intervention, is supported.
8.2 Successive Approximation ADC
The CY8C53 family of devices has a Successive Approximation (SAR) ADC. This ADC is 12-bit at up to 1 Msps, with single-ended or differential inputs, making it useful for a wide variety of sampling and control applications. 8.2.1 Functional Description In a SAR ADC an analog input signal is sampled and compared with the output of a DAC. A binary search algorithm is applied to the DAC and used to determine the output bits in succession from MSB to LSB. A block diagram of one SAR ADC is shown in Figure 8-3. Figure 8-3. SAR ADC Block Diagram
8.3 Comparators
The CY8C53 family of devices contains four comparators. Comparators have these features:
Input offset factory trimmed to less than 5 mV Rail-to-rail common mode input range (VSSA to VCCA)
vin vrefp vrefn
S/H DAC array D0:D11
comparator
SAR digital
D0:D11
Speed and power can be traded off by using one of three
modes: fast, slow, or ultra low power
Comparator outputs can be routed to look up tables to perform
autozero reset clock clock
simple logic functions and then can also be routed to digital blocks through a low pass filter. Two filters are provided and SC block outputs
The positive input of the comparators may be optionally passed Comparator inputs can be connections to GPIO, DAC outputs
POWER GROUND
power filtering
vrefp vrefn
8.3.1 Input and Output Interface The input is connected to the analog globals and muxes. The frequency of the clock is 16 times the sample rate; the maximum clock rate is 16 MHz. The positive and negative inputs to the comparators come from the analog global buses, the analog mux line, the analog local bus and precision reference through multiplexers. The output from each comparator could be routed to any of the two input LUTs. The output of that LUT is routed to the UDB Digital System Interface.
Document Number: 001-55035 Rev. *G
Page 50 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Figure 8-4. Analog Comparator
ANAIF
From Analog Routing
+ comp0 _
+
comp1
_
From Analog Routing
From Analog Routing
comp2
+ _
comp3
+ _
From Analog Routing
4
4
4
4
4
4
4
4
LUT0
LUT1
LUT2
LUT3
UDBs
8.3.2 LUT The CY8C53 family of devices contains four LUTs. The LUT is a two input, one output lookup table that is driven by any one or two of the comparators in the chip. The output of any LUT is routed to the digital system interface of the UDB array. From the digital system interface of the UDB array, these signals can be connected to UDBs, DMA controller, I/O, or the interrupt controller. The LUT control word written to a register sets the logic function on the output. The available LUT functions and the associated control word is shown in Table 8-1.
Table 8-1. LUT Function vs. Program Word and Inputs Control Word 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b Output (A and B are LUT inputs) FALSE (`0') A AND B A AND (NOT B) A (NOT A) AND B B A XOR B A OR B A NOR B A XNOR B NOT B A OR (NOT B) NOT A (NOT A) OR B A NAND B TRUE (`1')
Document Number: 001-55035 Rev. *G
Page 51 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
8.4 Opamps
The CY8C53 family of devices contain two general purpose opamps. Figure 8-5. Opamp
GPIO Analog Global Bus Analog Global Bus VREF Analog Internal Bus GPIO
The opamp has three speed modes, slow, medium, and fast. The slow mode consumes the least amount of quiescent power and the fast mode consumes the most power. The inputs are able to swing rail-to-rail. The output swing is capable of rail-to-rail operation at low current output, within 50 mV of the rails. When driving high current loads (about 25 mA) the output voltage may only get within 500 mV of the rails.
8.5 Programmable SC/CT Blocks
Opamp
GPIO
The CY8C53 family of devices contains two switched capacitor/continuous time (SC/CT) blocks in a device. Each switched capacitor/continuous time block is built around a single rail-to-rail high bandwidth opamp. Switched capacitor is a circuit design technique that uses capacitors plus switches instead of resistors to create analog functions. These circuits work by moving charge between capacitors by opening and closing different switches. Nonoverlapping in phase clock signals control the switches, so that not all switches are ON simultaneously. The PSoC Creator tool offers a user friendly interface, which allows you to easily program the SC/CT blocks. Switch control and clock phase control configuration is done by PSoC Creator so users only need to determine the application use parameters such as gain, amplifier polarity, VREF connection, and so on. The same opamps and block interfaces are also connectable to an array of resistors which allows the construction of a variety of continuous time functions. The opamp and resistor array is programmable to perform various analog functions including
Naked Operational Amplifier - Continuous Mode
=
Analog Switch
The opamp is uncommitted and can be configured as a gain stage or voltage follower on external or internal signals. See Figure 8-6. In any configuration, the input and output signals can all be connected to the internal global signals and monitored with an ADC, or comparator. The configurations are implemented with switches between the signals and GPIO pins. Figure 8-6. Opamp Configurations
a) Voltage Follower
Opamp Vin
Vout to Pin
Unity-Gain Buffer - Continuous Mode Programmable Gain Amplifier (PGA) - Continuous Mode Transimpedance Amplifier (TIA) - Continuous Mode
b) External Uncommitted Opamp
Up/Down Mixer - Continuous Mode Sample and Hold Mixer (NRZ S/H) - Switched Cap Mode First Order Analog to Digital Modulator - Switched Cap Mode
Opamp
Vout to GPIO
8.5.1 Naked Opamp The Naked Opamp presents both inputs and the output for connection to internal or external signals. The opamp has a unity gain bandwidth greater than 6.0 MHz and output drive current up to 650 A. This is sufficient for buffering internal signals (such as DAC outputs) and driving external loads greater than 7.5 kohms. 8.5.2 Unity Gain The Unity Gain buffer is a Naked Opamp with the output directly connected to the inverting input for a gain of 1.00. It has a -3 dB bandwidth greater than 6.0 MHz. 8.5.3 PGA The PGA amplifies an external or internal signal. The PGA can be configured to operate in inverting mode or noninverting mode. The PGA function may be configured for both positive and negative gains as high as 50 and 49 respectively. The gain is adjusted by changing the values of R1 and R2 as illustrated in Figure 8-7. The schematic in Figure 8-7 shows the configuration
Page 52 of 102
Vp to GPIO Vn to GPIO
c) Internal Uncommitted Opamp Vn
To Internal Signals
Opamp
Vout to Pin
Vp GPIO Pin
Document Number: 001-55035 Rev. *G
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
and possible resistor settings for the PGA. The gain is switched from inverting and non inverting by changing the shared select value of the both the input muxes. The bandwidth for each gain case is listed in Table 8-2. Table 8-2. Bandwidth Gain 1 24 48 50 Bandwidth 6.0 MHz 340 kHz 220 kHz 215 kHz
Figure 8-8. Continuous Time TIA Schematic
R fb
I in V ref V out
Figure 8-7. PGA Resistor Settings
R1 20 k or 40 k R2 20 k to 980 k
Vin Vref S Vref Vin
0 1
The TIA configuration is used for applications where an external sensor's output is current as a function of some type of stimulus such as temperature, light, magnetic flux etc. In a common application, the voltage DAC output can be connected to the VREF TIA input to allow calibration of the external sensor bias current by adjusting the voltage DAC output voltage.
8.6 LCD Direct Drive
0 1
The PGA is used in applications where the input signal may not be large enough to achieve the desired resolution in the ADC, or dynamic range of another SC/CT block such as a mixer. The gain is adjustable at runtime, including changing the gain of the PGA prior to each ADC sample. 8.5.4 TIA The Transimpedance Amplifier (TIA) converts an internal or external current to an output voltage. The TIA uses an internal feedback resistor in a continuous time configuration to convert input current to output voltage. For an input current Iin, the output voltage is Iin x Rfb +VREF, where VREF is the value placed on the non inverting input. The feedback resistor Rfb is programmable between 20 K and 1 M through a configuration register. Table 8-3 shows the possible values of Rfb and associated configuration settings. Table 8-3. Feedback Resistor Settings Configuration Word 000b 001b 010b 011b 100b 101b 110b 111b Nominal Rfb (K) 20 30 40 60 120 250 500 1000
The PSoC Liquid Crystal Display (LCD) driver system is a highly configurable peripheral designed to allow PSoC to directly drive a broad range of LCD glass. All voltages are generated on chip, eliminating the need for external components. With a high multiplex ratio of up to 1/16, the CY8C53 family LCD driver system can drive a maximum of 736 segments. The PSoC LCD driver module was also designed with the conservative power budget of portable devices in mind, enabling different LCD drive modes and power down modes to conserve power. PSoC Creator provides an LCD segment drive component. The component wizard provides easy and flexible configuration of LCD resources. You can specify pins for segments and commons along with other options. The software configures the device to meet the required specifications. This is possible because of the programmability inherent to PSoC devices. Key features of the PSoC LCD segment system are:
LCD panel direct driving Type A (standard) and Type B (low power) waveform support Wide operating voltage range support (2 V to 5 V) for LCD
panels
Static, 1/2, 1/3, 1/4, 1/5 bias voltage levels Internal bias voltage generation through internal resistor ladder Up to 62 total common and segment outputs Up to 1/16 multiplex for a maximum of 16 backplane/common
outputs
Up to 62 front plane/segment outputs for direct drive Drives up to 736 total segments (16 backplane x 46 front plane) Up to 64 levels of software controlled contrast Ability to move display data from memory buffer to LCD driver
through DMA (without CPU intervention)
Adjustable LCD refresh rate from 10 Hz to 150 Hz
Document Number: 001-55035 Rev. *G Page 53 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Ability to invert LCD display for negative image Three LCD driver drive modes, allowing power optimization LCD driver configurable to be active when PSoC is in limited
8.6.4 LCD DAC The LCD DAC generates the contrast control and bias voltage for the LCD system. The LCD DAC produces up to five LCD drive voltages plus ground, based on the selected bias ratio. The bias voltages are driven out to GPIO pins on a dedicated LCD bias bus, as required.
active mode
Figure 8-9. LCD System
Global Clock LCD DAC
8.7 CapSense
The CapSense system provides a versatile and efficient means for measuring capacitance in applications such as touch sense buttons, sliders, proximity detection, etc. The CapSense system uses a configuration of system resources, including a few hardware functions primarily targeted for CapSense. Specific resource usage is detailed in the CapSense component in PSoC Creator. A capacitive sensing method using a Delta-Sigma Modulator (CSD) is used. It provides capacitance sensing using a switched capacitor technique with a delta-sigma modulator to convert the sensing current to a digital code.
UDB LCD Driver Block DMA Display RAM
PIN
8.8 Temp Sensor
Die temperature is used to establish programming parameters for writing flash. Die temperature is measured using a dedicated sensor based on a forward biased transistor. The temperature sensor has its own auxiliary ADC.
PHUB
8.6.1 LCD Segment Pin Driver Each GPIO pin contains an LCD driver circuit. The LCD driver buffers the appropriate output of the LCD DAC to directly drive the glass of the LCD. A register setting determines whether the pin is a common or segment. The pin's LCD driver then selects one of the six bias voltages to drive the I/O pin, as appropriate for the display data. 8.6.2 Display Data Flow The LCD segment driver system reads display data and generates the proper output voltages to the LCD glass to produce the desired image. Display data resides in a memory buffer in the system SRAM. Each time you need to change the common and segment driver voltages, the next set of pixel data moves from the memory buffer into the Port Data Registers via DMA. 8.6.3 UDB and LCD Segment Control A UDB is configured to generate the global LCD control signals and clocking. This set of signals is routed to each LCD pin driver through a set of dedicated LCD global routing channels. In addition to generating the global LCD control signals, the UDB also produces a DMA request to initiate the transfer of the next frame of LCD data.
8.9 DAC
The CY8C53 parts contain two Digital to Analog Convertors (DACs). Each DAC is 8-bit and can be configured for either voltage or current output. The DACs support CapSense, power supply regulation, and waveform generation. Each DAC has the following features.
Adjustable voltage or current output in 255 steps Programmable step size (range selection) Eight bits of calibration to correct 25% of gain error Source and sink option for current output 8 Msps conversion rate for current output 1 Msps conversion rate for voltage output Monotonic in nature
Document Number: 001-55035 Rev. *G
Page 54 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Figure 8-10. DAC Block Diagram
I source Range 1x ,8x ,64x
Reference Source
Scaler
Vout R 3R I sink Range 1x ,8x ,64x
Iout
8.9.1 Current DAC The current DAC (IDAC) can be configured for the ranges 0 to 32 A, 0 to 256 A, and 0 to 2.048 mA. The IDAC can be configured to source or sink current. 8.9.2 Voltage DAC For the voltage DAC (VDAC), the current DAC output is routed through resistors. The two ranges available for the VDAC are 0 to 1.024 V and 0 to 4.096 V. In voltage mode any load connected to the output of a DAC should be purely capacitive (the output of the VDAC is not buffered).
oscillator frequency. The local oscillator frequency is provided by the selected clock source for the mixer. Continuous time up and down mixing works for applications with input signals and local oscillator frequencies up to 1 MHz. Figure 8-11. Mixer Configuration
C2 = 1.7 pF C1 = 850 fF
8.10 Up/Down Mixer
In continuous time mode, the SC/CT block components are used to build an up or down mixer. Any mixing application contains an input signal frequency and a local oscillator frequency. The polarity of the clock, Fclk, switches the amplifier between inverting or noninverting gain. The output is the product of the input and the switching function from the local oscillator, with frequency components at the local oscillator plus and minus the signal frequency (Fclk + Fin and Fclk - Fin) and reduced-level frequency components at odd integer multiples of the local
Rmix 0 20 k or 40 k Vin
0
Rmix 0 20 k or 40 k
sc_clk Vout
Vref sc_clk
1
Document Number: 001-55035 Rev. *G
Page 55 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
8.11 Sample and Hold
The main application for a sample and hold, is to hold a value stable while an ADC is performing a conversion. Some applications require multiple signals to be sampled simultaneously, such as for power calculations (V and I). Figure 8-12. Sample and Hold Topology (1 and 2 are opposite phases of a clock)
1
9. Programming, Debug Interfaces, Resources
The Cortex-M3 has internal debugging components, tightly integrated with the CPU, providing the following features:
JTAG or SWD access Flash Patch and Breakpoint (FPB) block for implementing
Vi
C1
1 2
C2
1
breakpoints and code patches
n
V ref V out
Data Watchpoint and Trigger (DWT) block for implementing
watchpoints, trigger resources, and system profiling
2
2
Embedded Trace Macrocell (ETM) for instruction trace Instrumentation Trace Macrocell (ITM) for support of printf-style
debugging
1 1 2 1
V ref
2
C3
C4
2
Vref
8.11.1 Down Mixer The S+H can be used as a mixer to down convert an input signal. This circuit is a high bandwidth passive sample network that can sample input signals up to 14 MHz. This sampled value is then held using the opamp with a maximum clock rate of 4 MHz. The output frequency is at the difference between the input frequency and the highest integer multiple of the Local Oscillator that is less than the input. 8.11.2 First Order Modulator - SC Mode A first order modulator is constructed by placing the switched capacitor block in an integrator mode and using a comparator to provide a 1-bit feedback to the input. Depending on this bit, a reference voltage is either subtracted or added to the input signal. The block output is the output of the comparator and not the integrator in the modulator case. The signal is downshifted and buffered and then processed by a decimator to make a delta-sigma converter or a counter to make an incremental converter. The accuracy of the sampled data from the first-order modulator is determined from several factors. The main application for this modulator is for a low frequency ADC with high accuracy. Applications include strain gauges, thermocouples, precision voltage, and current measurement
PSoC devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware. Four interfaces are available: JTAG, SWD, SWV, and TRACEPORT. JTAG and SWD support all programming and debug features of the device. JTAG also supports standard JTAG scan chains for board level test and chaining multiple JTAG devices for programming or testing. The SWV and TRACEPORT provide trace output from the DWT, ETM, and ITM. TRACEPORT is faster but uses more pins. SWV is slower but uses only one pin. Cortex-M3 debug and trace functionality enables full device debugging in the final system using the standard production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required to fully support debug. The PSoC Creator IDE software provides fully integrated programming and debug support for PSoC devices. The low cost MiniProg3 programmer and debugger is designed to provide full programming and debug support of PSoC devices in conjunction with the PSoC Creator IDE. PSoC JTAG, SWD, and SWV interfaces are fully compatible with industry standard third party tools. All Cortex-M3 debug and trace modules are disabled by default and can only be enabled in firmware. If not enabled, the only way to reenable them is to erase the entire device, clear flash protection, and reprogram the device with new firmware that enables them. Disabling debug and trace features, robust flash protection, and hiding custom analog and digital functionality inside the PSoC device provide a level of security not possible with multichip application solutions. Additionally, all device interfaces can be permanently disabled (Device Security) for applications concerned about phishing attacks due to a maliciously reprogrammed device. Permanently disabling interfaces is not recommended in most applications because the designer then cannot access the device. Because all programming, debug, and test interfaces are disabled when Device Security is enabled, PSoCs with Device Security enabled may not be returned for failure analysis.
Document Number: 001-55035 Rev. *G
Page 56 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
9.1 JTAG Interface
The IEEE 1149.1 compliant JTAG interface exists on four or five pins (the nTRST pin is optional). The JTAG clock frequency can be up to 8 MHz, or 1/3 of the CPU clock frequency for 8 and 16-bit transfers, or 1/5 of the CPU clock frequency for 32-bit transfers, whichever is least. By default, the JTAG pins are enabled on new devices but the JTAG interface can be disabled, allowing these pins to be used as General Purpose I/O (GPIO) instead. The JTAG interface is used for programming the flash memory, debugging, I/O scan chains, and JTAG device chaining.
9.4 Trace Features
The following trace features are supported:
Instruction trace Data watchpoint on access to data address, address range, or
data value
Trace trigger on data watchpoint Debug exception trigger Code profiling Counters for measuring clock cycles, folded instructions,
9.2 SWD Interface
The SWD interface is the preferred alternative to the JTAG interface. It requires only two pins instead of the four or five needed by JTAG. SWD provides all of the programming and debugging features of JTAG at the same speed. SWD does not provide access to scan chains or device chaining. The SWD clock frequency can be up to 1/3 of the CPU clock frequency. SWD uses two pins, either two of the JTAG pins (TMS and TCK) or the USBIO D+ and D- pins. The USBIO pins are useful for in system programming of USB solutions that would otherwise require a separate programming connector. One pin is used for the data clock and the other is used for data input and output. SWD can be enabled on only one of the pin pairs at a time. This only happens if, within 8 s (key window) after reset, that pin pair (JTAG or USB) receives a predetermined sequence of 1s and 0s. SWD is used for debugging or for programming the flash memory. The SWD interface can be enabled from the JTAG interface or disabled, allowing its pins to be used as GPIO. Unlike JTAG, the SWD interface can always be reacquired on any device during the key window. It can then be used to reenable the JTAG interface, if desired. When using SWD or JTAG pins as standard GPIO, make sure that the GPIO functionality and PCB circuits do not interfere with SWD or JTAG use.
load/store operations, sleep cycles, cycles per instruction, interrupt overhead
Interrupt events trace Software event monitoring, "printf-style" debugging
9.5 SWV and TRACEPORT Interfaces
The SWV and TRACEPORT interfaces provide trace data to a debug host via the Cypress MiniProg3 or an external trace port analyzer. The 5 pin TRACEPORT is used for rapid transmission of large trace streams. The single pin SWV mode is used to minimize the number of trace pins. SWV is shared with a JTAG pin. If debugging and tracing are done at the same time then SWD may be used with either SWV or TRACEPORT, or JTAG may be used with TRACEPORT, as shown in Table 9-1. Table 9-1. Debug Configurations Debug and Trace Configuration All debug and trace disabled JTAG SWD SWV TRACEPORT JTAG + TRACEPORT SWD + SWV SWD + TRACEPORT GPIO Pins Used 0 4 or 5 2 1 5 9 or 10 3 7
9.3 Debug Features
The CY8C53 supports the following debug features:
Halt and single-step the CPU View and change CPU and peripheral registers, and RAM
addresses
Six program address breakpoints and two literal access
breakpoints
Data watchpoint events to CPU Patch and remap instruction from flash to SRAM Debugging at the full speed of the CPU Debug operations are possible while the device is reset, or in
9.6 Programming Features
The JTAG and SWD interfaces provide full programming support. The entire device can be erased, programmed, and verified. Designers can increase flash protection levels to protect firmware IP. Flash protection can only be reset after a full device erase. Individual flash blocks can be erased, programmed, and verified, if block security settings permit.
low power modes debugger
Compatible with PSoC Creator and MiniProg3 programmer and Standard JTAG programming and debugging interfaces make
9.7 Device Security
PSoC 5 offers an advanced security feature called device security, which permanently disables all test, programming, and debug ports, protecting your application from external access. The device security is activated by programming a 32-bit key (0x50536F43) to a Write Once Latch (WOL).
CY8C53 compatible with other popular third-party tools (for example, ARM / Keil)
Document Number: 001-55035 Rev. *G
Page 57 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
The Write Once Latch is a type of nonvolatile latch (NVL). The cell itself is an NVL with additional logic wrapped around it. Each WOL device contains four bytes (32 bits) of data. The wrapper outputs a `1' if a super-majority (28 of 32) of its bits match a pre-determined pattern (0x50536F43); it outputs a `0' if this majority is not reached. When the output is 1, the Write Once NV latch locks the part out of Debug and Test modes; it also permanently gates off the ability to erase or alter the contents of the latch. Matching all bits is intentionally not required, so that single (or few) bit failures do not deassert the WOL output. The state of the NVL bits after wafer processing is truly random with no tendency toward 1 or 0. The WOL only locks the part after the correct 32-bit key (0x50536F43) is loaded into the NVL's volatile memory, programmed into the NVL's nonvolatile cells, and the part is reset. The output of the WOL is only sampled on reset and used to disable the access. This precaution prevents anyone from reading, erasing, or altering the contents of the internal memory. The user can write the key into the WOL to lock out external access only if no flash protection is set (see "Flash Security" section on page 16). However, after setting the values in the WOL, a user still has access to the part until it is reset. Therefore, a user can write the key into the WOL, program the flash protection data, and then reset the part to lock it. If the device is protected with a WOL setting, Cypress cannot perform failure analysis and, therefore, cannot accept RMAs from customers. The WOL can be read out via Serial Wire Debug (SWD) port to electrically identify protected parts. The user can write the key in WOL to lock out external access only if no flash protection is set. For more information on how to take full advantage of the security features in PSoC see the PSoC 5 TRM. Disclaimer Note the following details of the flash code protection features on Cypress devices. Cypress products meet the specifications contained in their particular Cypress datasheets. Cypress believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Cypress is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress are committed to continuously improving the code protection features of our products.
10. Development Support
The CY8C53 family has a rich set of documentation, development tools, and online resources to assist you during your development process. Visit psoc.cypress.com/getting-started to find out more.
10.1 Documentation
A suite of documentation, to ensure that you can find answers to your questions quickly, supports the CY8C53 family. This section contains a list of some of the key documents. Software User Guide: A step-by-step guide for using PSoC Creator. The software user guide shows you how the PSoC Creator build process works in detail, how to use source control with PSoC Creator, and much more. Component Datasheets: The flexibility of PSoC allows the creation of new peripherals (components) long after the device has gone into production. Component datasheets provide all of the information needed to select and use a particular component, including a functional description, API documentation, example code, and AC/DC specifications. Application Notes: PSoC application notes discuss a particular application of PSoC in depth; examples include brushless DC motor control and on-chip filtering. Application notes often include example projects in addition to the application note document. Technical Reference Manual: PSoC Creator makes designing with PSoC as easy as dragging a peripheral onto a schematic, but, when low level details of the PSoC device are required, use the technical reference manual (TRM) as your guide. Note Visit www.arm.com for detailed documentation about the Cortex-M3 CPU.
10.2 Online
In addition to print documentation, the Cypress PSoC forums connect you with fellow PSoC users and experts in PSoC from around the world, 24 hours a day, 7 days a week.
10.3 Tools
With industry standard cores, programming, and debugging interfaces, the CY8C53 family is part of a development tool ecosystem. Visit us at www.cypress.com/go/psoccreator for the latest information on the revolutionary, easy to use PSoC Creator IDE, supported third party compilers, programmers, debuggers, and development kits.
Document Number: 001-55035 Rev. *G
Page 58 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
11. Electrical Specifications
Specifications are valid for -40 C TA 85 C and TJ 100 C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC Creator components, see the component datasheets for full AC/DC specifications of individual functions. See the "Example Peripherals" section on page 34 for further explanation of PSoC Creator components.
11.1 Absolute Maximum Ratings
Table 11-1. Absolute Maximum Ratings DC Specifications Parameter TSTG Description Storage temperature Conditions Higher storage temperatures reduce NVL data retention time. Recommended storage temperature is +25 C 25 C. Extended duration storage temperatures above 85 C degrade reliability. Min -55 Typ 25 Max 100 Units C
VDDA VDDD VDDIO VCCA VCCD VSSA VGPIO[9] VSIO VIND VBAT Ivddio ESDHBM ESDCDM
Analog supply voltage relative to VSSA Digital supply voltage relative to VSSD I/O supply voltage relative to VSSD Direct analog core voltage input Direct digital core voltage input Analog ground voltage DC input voltage on GPIO DC input voltage on SIO Voltage at boost converter input Boost converter supply Current per VDDIO supply pin Electrostatic discharge voltage ESD voltage Human body model Charge device model Includes signals sourced by VDDA and routed internal to the pin. Output disabled Output enabled
-0.5 -0.5 -0.5 -0.5 -0.5 VSSD - 0.5 VSSD - 0.5 VSSD - 0.5 VSSD - 0.5 0.5 VSSD - 0.5 - 2200 500
- - - - - - - - - - - - - -
6 6 6 1.95 1.95 VSSD + 0.5 VDDIO + 0.5 7 6 5.5 5.5 100 - -
V V V V V V V V V V V mA V V
Note Usage above the absolute maximum conditions listed in Table 11-1 may cause permanent damage to the device. Exposure to maximum conditions for extended periods of time may affect device reliability. When used below maximum conditions but above normal operating conditions the device may not operate to specification.
Note 9. The VDDIO supply voltage must be greater than the maximum analog voltage on the associated GPIO pins. Maximum analog voltage on GPIO pin VDDIO VDDA.
Document Number: 001-55035 Rev. *G
Page 59 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
11.2 Device Level Specifications
Specifications are valid for -40 C TA 85 C and TJ 100 C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. 11.2.1 Device Level Specifications Table 11-2. DC Specifications Parameter Description VDDA Analog supply voltage and input to analog core regulator VDDA Analog supply voltage, analog regulator bypassed VDDD Digital supply voltage relative to VSSD Digital supply voltage, digital VDDD regulator bypassed VDDIO[10] VCCA VCCD VBAT IDD[11] Conditions Analog core regulator enabled Analog core regulator disabled Digital core regulator enabled Digital core regulator disabled Min 1.8 1.71 1.8 1.71 1.71 1.71 1.71 0.5 - - - - - - - - - - - - - Typ - 1.8 - 1.8 - 1.8 1.8 - - 2 - - - - - 2 - - - - - Max 5.5 1.89 VDDA 1.89 VDDA 1.89 1.89 5.5 - - - - - - - - - - - - - Units V V V V V V V V mA mA mA A A A A A A A A A A
I/O supply voltage relative to VSSIO Direct analog core voltage input Analog core regulator disabled (Analog regulator bypass) Direct digital core voltage input Digital core regulator disabled (Digital regulator bypass) Voltage supplied to boost converter Active Mode, VDD = 1.71 V - 5.5 V T = -40 C Execute from Flash cache, see Cache Controller on page 12 and T = 25 C Flash Program Memory on page 16 T = 85 C [12] Sleep Mode VDD = VDDIO = 4.5-5.5 V T = -40 C CPU = OFF RTC = ON (= ECO32K ON, in low T = 25 C power mode) T = 85 C Sleep timer = ON (= ILO ON at 1 kHz)[13] VDD = VDDIO = 2.7-3.6 V T = -40 C WDT = OFF T = 25 C I2C Wake = OFF T = 85 C Comparator = OFF POR = ON VDD = VDDIO = 1.71-1.95 V T = -40 C Boost = OFF T = 25 C SIO pins in single ended input, T = 85 C unregulated output mode Comparator = ON CPU = OFF RTC = OFF Sleep timer = OFF WDT = OFF I2C Wake = OFF POR = ON Boost = OFF SIO pins in single ended input, unregulated output mode VDD = VDDIO = 2.7-3.6V T = 25 C
Notes 10. The VDDIO supply voltage must be greater than the maximum analog voltage on the associated GPIO pins. Maximum analog voltage on GPIO pin VDDIO VDDA. 11. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective datasheets, available in PSoC Creator, the integrated design environment. To compute total current, find CPU current at frequency of interest and add peripheral currents for your particular system from the device datasheet and component datasheets 12. If VCCD and VCCA are externally regulated, the voltage difference between VCCD and VCCA must be less than 50 mV. 13. Sleep timer generates periodic interrupts to wake up the CPU. This specification applies only to those times that the CPU is off.
Document Number: 001-55035 Rev. *G
Page 60 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Table 11-2. DC Specifications (continued) Parameter Description I2C Wake = ON CPU = OFF RTC = OFF Sleep timer = OFF WDT = OFF Comparator = OFF POR = ON Boost = OFF SIO pins in single ended input, unregulated output mode Hibernate Mode[14] VDD = VDDIO = 4.5-5.5 V Hibernate mode current All regulators and oscillators off. SRAM retention GPIO interrupts are active Boost = OFF SIO pins in single ended input, unregulated output mode T = -40 C T = 25 C T = 85 C - - - - - - - - - - - - - 300 - - - - - - - - - - - - - nA nA nA nA nA nA nA nA nA Conditions VDD = VDDIO = 2.7-3.6V T = 25 C Min - Typ - Max - Units A
VDD = VDDIO = 2.7-3.6 V
T = -40 C T = 25 C T = 85 C VDD = VDDIO = 1.71-1.95 V T = -40 C T = 25 C T = 85 C
Table 11-3. AC Specifications[15] Parameter FCPU FBUSCLK Svdd TIO_INIT TSTARTUP Description CPU frequency Bus frequency VDD ramp rate Time from VDDD/VDDA/VCCD/VCCA IPOR to I/O ports set to their reset states Time from VDDD/VDDA/VCCD/VCCA VCCA/VDDA = regulated from PRES to CPU executing code at VDDA/VDDD, no PLL used, fast IMO reset vector boot mode (48 MHz typ.) VCCA/VCCD = regulated from VDDA/VDDD, no PLL used, slow IMO boot mode (12 MHz typ.) TSLEEP Wakeup from limited active mode - Application of non-LVD interrupt to beginning of execution of next CPU instruction Wakeup from sleep mode - Occurrence of LVD interrupt to beginning of execution of next CPU instruction THIBERNATE Wakeup form hibernate mode - Application of external interrupt to beginning of execution of next CPU instruction Conditions 1.71 V VDDD 5.5 V 1.71 V VDDD 5.5 V Min DC DC - - Typ - - - - Max 80 80 1 10 Units MHz MHz V/ns s
-
-
33
s
-
-
66
s
-
-
12
s
-
-
15
s
-
-
100
s
Notes 14. If VCCD and VCCA are externally regulated, the voltage difference between VCCD and VCCA must be less than 50 mV. 15. Based on device characterization (Not production tested).
Document Number: 001-55035 Rev. *G
Page 61 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
11.3 Power Regulators
Specifications are valid for -40 C TA 85 C and TJ 100 C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. 11.3.1 Digital Core Regulator Table 11-4. Digital Core Regulator DC Specifications Parameter Description Input voltage VDDD VCCD Output voltage Regulator output capacitor Conditions Min 1.8 - - Typ - 1.80 1 Max 5.5 - - Units V V F
10%, X5R ceramic or better. The two VCCD pins must be shorted together, with as short a trace as possible, see Power System on page 23
11.3.2 Analog Core Regulator Table 11-5. Analog Core Regulator DC Specifications Parameter Description Input voltage VDDA VCCA Output voltage Regulator output capacitor 11.3.3 Inductive Boost Regulator Table 11-6. Inductive Boost Regulator DC Specifications Parameter Description Input voltage VBAT Conditions Includes startup VIN=1.6-5.5 V, VOUT =1.6-5.0 V, external diode VIN=1.6-3.6 V, VOUT =1.6-3.6 V, internal diode VIN=0.8-1.6 V, VOUT =1.6-3.6 V, internal diode VIN=0.8-1.6 V, VOUT =3.6-5.0 V, external diode VIN=0.5-0.8 V, VOUT =1.6-3.6 V, internal diode 10 H specified 22 F || 0.1 F specified External Schottky diode is required for VBOOST > 3.6 V External Schottky diode is required for VBOOST > 3.6 V Boost active mode Boost standby mode, 32 khz external crystal oscillator, IBOOST < 1 A Min 0.5 - - - - - 4.7 10 1 20 - - - Typ - - - - - - 10 22 - - - 200 12 Max 5.5 50 75 30 20 15 47 47 - - 700 - - Units V mA mA mA mA mA H F A V mA A A Conditions Min 1.8 - - Typ - 1.80 1 Max 5.5 - - Units V V F
10%, X5R ceramic or better
IBOOST
Load current[16, 17]
LBOOST CBOOST IF VR ILPK
Boost inductor Filter capacitor[18] External Schottky diode average forward current External Schottky diode peak reverse voltage Inductor peak current Quiescent current
Notes 16. For output voltages above 3.6 V, an external diode is required. 17. Maximum output current applies for output voltages 4x input voltage. 18. Based on device characterization (Not production tested).
Document Number: 001-55035 Rev. *G
Page 62 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Table 11-6. Inductive Boost Regulator DC Specifications (continued) Parameter Description Boost output voltage range[19] 1.8 V 1.9 V 2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V 5.0 V Load regulation Line regulation Efficiency Conditions Min 1.71 1.81 1.90 2.28 2.57 2.85 3.14 3.42 4.75 - - 90 Typ 1.80 1.90 2.00 2.40 2.70 3.00 3.30 3.60 5.00 - - - Max 1.89 2.00 2.10 2.52 2.84 3.15 3.47 3.8 5.25 TBD TBD - Units V V V V V V V V V % % %
VBOOST
External diode required
VBAT = 2.4 V, VOUT = 2.7 V, IOUT = 10 mA, Fsw = 400 kHz
Table 11-7. Inductive Boost Regulator AC Specifications Parameter Description VRIPPLE Ripple voltage (peak-to-peak) FSW Switching frequency Duty cycle Conditions VOUT = 1.8 V, FSW = 400 kHz, IOUT = 10 mA Min - - 20 Typ - 0.1, 0.4, or 2 - Max 100 - 80 Units mV MHz %
11.4 Inputs and Outputs
Specifications are valid for -40 C TA 85 C and TJ 100 C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. 11.4.1 GPIO Table 11-8. GPIO DC Specifications Parameter VIH VIL VIH VIH VIL VIL VOH VOL Rpullup Description Input voltage high threshold Input voltage low threshold Input voltage high threshold Input voltage high threshold Input voltage low threshold Input voltage low threshold Output voltage high Output voltage low Pull-up resistor Conditions CMOS Input, PRT[x]CTL = 0 CMOS Input, PRT[x]CTL = 0 Min 0.7 VDDIO - Typ - - - - - - - - - - 5.6 Max - 0.3 VDDIO - - 0.3 x VDDIO 0.8 - - 0.6 0.6 8 Units V V V V V V V V V V k
LVTTL Input, PRT[x]CTL = 1,VDDIO 0.7 x VDDIO < 2.7 V LVTTL Input, PRT[x]CTL = 1, 2.0 VDDIO 2.7 V LVTTL Input, PRT[x]CTL = 1,VDDIO - < 2.7 V - LVTTL Input, PRT[x]CTL = 1, VDDIO 2.7 V IOH = 4 mA at 3.3 VDDIO VDDIO - 0.6 IOH = 1 mA at 1.8 VDDIO IOL = 8 mA at 3.3 VDDIO IOL = 4 mA at 1.8 VDDIO VDDIO - 0.5 - - 4
Note 19. Based on device characterization (Not production tested).
Document Number: 001-55035 Rev. *G
Page 63 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Table 11-8. GPIO DC Specifications (continued) Parameter Rpulldown IIL CIN VH Idiode Rglobal Rmux Description Pull-down resistor Input leakage current (absolute value)[20] Input capacitance[20] Conditions 25C, VDDIO = 3.0 V GPIOs without opamp outputs GPIOs with opamp outputs Min 4 - - - - - - - Typ 5.6 - - - 40 - 320 220 Max 8 2 7 18 - 100 - - Units k nA pF pF mV A
Input voltage hysteresis (Schmitt-Trigger)[20] Current through protection diode to VDDIO and VSSIO Resistance pin to analog global bus 25 C, VDDIO = 3.0 V Resistance pin to analog mux bus 25 C, VDDIO = 3.0 V
Table 11-9. GPIO AC Specifications Parameter TriseF TfallF TriseS TfallS Description Rise time in Fast Strong Mode[20] Fall time in Fast Strong Mode[20] Rise time in Slow Strong Mode[20] Fall time in Slow Strong Mode[20] GPIO output operating frequency 3.3 V < VDDIO < 5.5 V, fast strong drive mode 1.71 V < VDDIO < 3.3 V, fast strong drive mode Conditions 3.3 V VDDIO Cload = 25 pF 3.3 V VDDIO Cload = 25 pF 3.3 V VDDIO Cload = 25 pF 3.3 V VDDIO Cload = 25 pF 90/10% VDDIO into 25 pF 90/10% VDDIO into 25 pF Min 2 2 10 10 - - - - Typ - - - - - - - - Max 12 12 60 60 33 20 7 3.5 Units ns ns ns ns MHz MHz MHz MHz
Fgpioout
3.3 V < VDDIO < 5.5 V, slow strong 90/10% VDDIO into 25 pF drive mode 1.71 V < VDDIO < 3.3 V, slow strong 90/10% VDDIO into 25 pF drive mode GPIO input operating frequency 1.71 V < VDDIO < 5.5 V 90/10% VDDIO
Fgpioin 11.4.2 SIO
-
-
66
MHz
Table 11-10. SIO DC Specifications Parameter Vinref Description Conditions Input voltage reference (Differential input mode) Output voltage reference (Regulated output mode) VDDIO > 3.7 VDDIO < 3.7 VIH Input voltage high threshold GPIO mode Differential input mode Input voltage low threshold GPIO mode Differential input mode CMOS input Hysteresis disabled CMOS input Hysteresis disabled Min 0.5 Typ Max Units - 0.52 VDDIO V
Voutref
1 1 0.7 VDDIO Vinref + 0.1 - -
- - - - - -
VDDIO - 1 VDDIO - 0.5 - - 0.3 VDDIO Vinref - 0.1
V V V V V V
VIL
Note 20. Based on device characterization (Not production tested).
Document Number: 001-55035 Rev. *G
Page 64 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Table 11-10. SIO DC Specifications (continued) Parameter Description Output voltage high Unregulated mode Regulated mode Regulated mode Output voltage low Conditions IOH = 4 mA, VDDIO = 3.3 V IOH = 1 mA IOH = 0.1 mA VDDIO = 3.30 V, IOL = 25 mA VDDIO = 1.80 V, IOL = 4 mA Pull-up resistor Pull-down resistor Input leakage current (absolute value)[21] VIH < Vddsio VIH > Vddsio Input Capacitance[21] Input voltage hysteresis (Schmitt-Trigger)[21] Current through protection diode to VSSIO Min VDDIO - 0.4 Voutref - 0.6 Voutref - 0.25 - - 4 4 Typ - - - - - 5.6 5.6 Max - Voutref+0.2 Voutref+0.2 0.8 0.4 8 8 Units V V V V V k k
VOH
VOL Rpullup Rpulldown IIL
25 C, Vddsio = 3.0 V, VIH = 3.0 V 25 C, Vddsio = 0 V, VIH = 3.0 V Single ended mode (GPIO mode) Differential mode
CIN VH Idiode
- - - - - -
- - - 40 50 -
14 10 7 - - 100
nA A pF mV mV A
Table 11-11. SIO AC Specifications Parameter TriseF TfallF TriseS TfallS Description Rise time in Fast Strong Mode (90/10%)[21] Fall time in Fast Strong Mode (90/10%)[21] Rise time in Slow Strong Mode (90/10%)[21] Fall time in Slow Strong Mode (90/10%)[21] Conditions Cload = 25 pF, VDDIO = 3.3 V Cload = 25 pF, VDDIO = 3.3 V Cload = 25 pF, VDDIO = 3.0 V Cload = 25 pF, VDDIO = 3.0 V Min 1 1 10 10 Typ - - - - Max 12 12 75 60 Units ns ns ns ns
Note 21. Based on device characterization (Not production tested).
Document Number: 001-55035 Rev. *G
Page 65 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Table 11-11. SIO AC Specifications (continued) Parameter Description Conditions SIO output operating frequency 3.3 V < VDDIO < 5.5 V, Unregulated 90/10% VDDIO into 25 pF output (GPIO) mode, fast strong drive mode 1.71 V < VDDIO < 3.3 V, Unregu90/10% VDDIO into 25 pF lated output (GPIO) mode, fast strong drive mode 3.3 V < VDDIO < 5.5 V, Unregulated 90/10% VDDIO into 25 pF output (GPIO) mode, slow strong drive mode 1.71 V < VDDIO < 3.3 V, Unregulated output (GPIO) mode, slow strong drive mode 90/10% VDDIO into 25 pF Min - Typ - Max 33 Units MHz
-
-
16
MHz
-
-
5
MHz
Fsioout
-
-
4
MHz
3.3 V < VDDIO < 5.5 V, Regulated Output continuously switching output mode, fast strong drive mode into 25 pF 1.71 V < VDDIO < 3.3 V, Regulated output mode, fast strong drive mode 1.71 V < VDDIO < 5.5 V, Regulated output mode, slow strong drive mode Fsioin SIO input operating frequency 1.71 V < VDDIO < 5.5 V Output continuously switching into 25 pF Output continuously switching into 25 pF
- - -
- - -
20 10 2.5
MHz MHz MHz
90/10% VDDIO
-
-
66
MHz
Document Number: 001-55035 Rev. *G
Page 66 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
11.4.3 USBIO For operation in USB mode, VDDD range condition is 3.15 V VDDD 3.45 V (USB regulator bypassed) or 4.35 V VDDD 5.25 V (USB regulator in use). For operation in GPIO mode, the standard range for VDDD applies, see Device Level Specifications on page 60. Table 11-12. USBIO DC Specifications Parameter Rusbi Rusba Vohusb Volusb Vohgpio Volgpio Vdi Vcm Vse Rps2 Rext Zo CIN IIL Description USB D+ pull-up resistance USB D+ pull-up resistance Static output high Static output low Output voltage high, GPIO mode Output voltage low, GPIO mode Differential input sensitivity Differential input common mode range Single ended receiver threshold PS/2 pull-up resistance External USB series resistor USB driver output impedance USB transceiver input capacitance Input leakage current (absolute value) 25 C, VDDD = 3.0 V In PS/2 mode, with PS/2 pull-up enabled In series with each USB pin Including Rext Conditions With idle bus While receiving traffic 15 k 5% to Vss, internal pull-up enabled 15 k 5% to Vss, internal pull-up enabled IOH = 4 mA, VDDD 3 V IOL = 4 mA, VDDD 3 V |(D+)-(D-)| Min 0.900 1.425 2.8 - 2.4 - - 0.8 0.8 3 21.78 (-1%) 28 - - Typ - - - - - - - - - - 22 - - - Max 1.575 3.090 3.6 0.3 - 0.3 0.2 2.5 2 7 22.22 (+1%) 44 20 2 Units k k V V V V V V V k pF nA
Table 11-13. USBIO AC Specifications Parameter Description Tdrate Full-speed data rate average bit rate Tjr1 Tjr2 Tdj1 Tdj2 Tfdeop Tfeopt Tfeopr Tfst Fgpio_out Tr_gpio Tf_gpio Receiver data jitter tolerance to next transition Receiver data jitter tolerance to pair transition Driver differential jitter to next transition Driver differential jitter to pair transition Source jitter for differential transition to SE0 transition Source SE0 interval of EOP Receiver SE0 interval of EOP Width of SE0 interval during differential transition GPIO mode output operating frequency 3 V VDDD 5.5 V VDDD = 1.71 V Rise time, GPIO mode, 10%/90% VDDD VDDD > 3 V, 25 pF load VDDD = 1.71 V, 25 pF load Fall time, GPIO mode, 90%/10% VDDD VDDD > 3 V, 25 pF load VDDD = 1.71 V, 25 pF load Conditions Min 12 - 0.25% -8 -5 -3.5 -4 -2 160 82 - - - 1 4 1 4 Typ 12 - - - - - - - - - - - - - - Max 12 + 0.25% 8 5 3.5 4 5 175 - 14 20 6 12 40 12 40 Units MHz ns ns ns ns ns ns ns ns MHz MHz ns ns ns ns
Document Number: 001-55035 Rev. *G
Page 67 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Table 11-14. USB Driver AC Specifications Parameter Tr Tf TR Vcrs 11.4.4 XRES Table 11-15. XRES DC Specifications Parameter VIH VIL Rpullup CIN VH Idiode Description Input voltage high threshold Input voltage low threshold Pull-up resistor Input capacitance[22] Input voltage hysteresis (Schmitt-Trigger)[22] Current through protection diode to VDDIO and VSSIO Conditions CMOS Input, PRT[x]CTL = 0 CMOS Input, PRT[x]CTL = 0 Min 0.7 VDDIO - 4 - - - Typ - - 5.6 3 100 - Max - 0.3 VDDIO 8 - - 100 Units V V k pF mV A Description Transition rise time Transition fall time Rise/fall time matching Output signal crossover voltage Conditions Min 4 4 90% 1.3 Typ - - - - Max 20 20 111% 2 V Units ns ns
Table 11-16. XRES AC Specifications Parameter TRESET Description Reset pulse width Conditions Min 1 Typ - Max - Units s
Note 22. Based on device characterization (Not production tested).
Document Number: 001-55035 Rev. *G
Page 68 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
11.5 Analog Peripherals
Specifications are valid for -40 C TA 85 C and TJ 100 C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. 11.5.1 Opamp Table 11-17. Opamp DC Specifications Parameter VIOFF VIOFF TCVos Ge1 VI VO IOUT Description Conditions Input offset voltage Input offset voltage T = 25 C Input offset voltage drift with temperature Gain error, unity gain buffer mode Rload = 1 k Quiescent current Input voltage range Output voltage range Output load = 1 mA Output current Output voltage is between VSSA +500 mV and VDDA - 500 mV, and VDDA > 2.7 V Output voltage is between VSSA +500 mV and VDDA - 500 mV, and VDDA > 1.7 V and VDDA < 2.7 V Min - - - - - VSSA VSSA + 50 25 Typ - 0.5 12 - 900 - - - Max Units 2 mV - mV - v/C 0.1 % - A VDDA mV VDDA - 50 mV - mA
IOUT CMRR
Output current Common mode rejection ratio[23]
16
-
-
mA
70
-
-
dB
Table 11-18. Opamp AC Specifications Parameter Description GBW Gain BW[23] Tslew Slew rate[23] Input noise density[23] Conditions 100 mV pk-pk, load capacitance 200 pF Load capacitance 200 pF Min 3 3 - Typ - - 38 Max - - - Units MHz V/s nv/sqrtHz
11.5.2 Voltage Reference Table 11-19. Voltage Reference Specifications Parameter VREF Description Precision reference voltage Temperature drift[23] Long term drift Thermal cycling drift (stability)[23] Total variation[23] 50 100 1 Conditions Initial trimming Min 1.023 (-0.1%) Typ 1.024 Max 1.025 (+0.1%) 15 Units V ppm/C ppm/Khr ppm %
Note 23. Based on device characterization (Not production tested).
Document Number: 001-55035 Rev. *G
Page 69 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
11.5.3 SAR ADC Table 11-20. SAR ADC DC Specifications Parameter Resolution Number of channels - single ended Number of channels - differential Monotonicity[24] Gain error Input offset voltage Current consumption Input voltage range - single ended[24] Input voltage range - differential[24] Input CIN resistance[24] Input capacitance[24] Differential pair is formed using a pair of neighboring GPIO. Description Conditions Min - - - Yes - - - VSSA VSSA - 7 Typ - - - - - - - - - - 8 Max 12 No of GPIO No of GPIO/2 - 0.1 0.2 500 VDDA VDDA 2 9 % mV A V V K pF Units bits
Table 11-21. SAR ADC AC Specifications Parameter PSRR CMRR SNR INL DNL THD Description Sample & hold droop[24] Power supply rejection ratio[24] Common mode rejection ratio Sample rate[24] Signal-to-noise ratio (SNR)[24] Input bandwidth[24] Integral non linearity[24] Differential non linearity[24] Total harmonic distortion[24] Internal reference Internal reference Conditions Min - 80 80 - 70 - - - - Typ - - - - - 500 - - - Max 1 - - 1 - -
1 1
Units V/s dB dB Msps dB KHz LSB LSB %
0.005
11.5.4 Analog Globals Table 11-22. Analog Globals AC Specifications Parameter Rppag Rppmuxbus BWag CMRRag Description Resistance pin-to-pin through analog global[25] Resistance pin-to-pin through analog mux bus[25] 3 dB bandwidth of analog globals Common mode rejection for differential signals Conditions VDDA = 3.0 V VDDA = 3.0 V VDDA = 3.0 V VDDA = 3.0 V Min - - - 85 Typ 939 721 - 91 Max 1461 1135 2 - Units MHz dB
Notes 24. Based on device characterization (Not production tested). 25. The resistance of the analog global and analog mux bus is high if VDDA 2.7 V, and the chip is in either sleep or hibernate mode. Use of analog global and analog mux bus under these conditions is not recommended.
Document Number: 001-55035 Rev. *G
Page 70 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
11.5.5 Comparator Table 11-23. Comparator DC Specifications Parameter VIOFF VIOFF VIOFF VHYST VICM CMRR ICMP Description Input offset voltage in fast mode Input offset voltage in slow mode Input offset voltage in fast mode[26] Conditions Factory trim Factory trim Custom trim Min - - - - - Hysteresis enable mode Fast mode Slow mode Common mode rejection ratio High current mode/fast mode[27] Low current mode/slow mode[27] Ultra low power mode[27] - 0 0 50 - - - Typ - - - - 12 10 - - - - - 6 Max
2 2
Units mV mV mV mV mV mV V V dB A A A
2 1 - 32 VDDA- 0.1 VDDA - 400 100 -
Input offset voltage in slow mode[26] Custom trim Input offset voltage in ultra low power mode Hysteresis Input common mode voltage
Table 11-24. Comparator AC Specifications Parameter Description Response time, high current mode[27] TRESP Response time, low current mode[27] Response time, ultra low power mode[27] Conditions 50 mV overdrive, measured pin-to-pin 50 mV overdrive, measured pin-to-pin 50 mV overdrive, measured pin-to-pin Min - - - Typ 95 155 55 Max TBD TBD - Units ns ns s
Notes 26. The recommended procedure for using a custom trim value for the on-chip comparators are found in the TRM. 27. Based on device characterization (Not production tested).
Document Number: 001-55035 Rev. *G
Page 71 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
11.5.6 IDAC Table 11-25. IDAC (Current Digital-to-Analog Converter) DC Specifications Parameter Resolution IOUT Output current High[28] Code = 255, VDDA 2.7 V, RL 600 Code = 255, VDDA 2.7 V, RL 300 Medium[28] Low[28] INL DNL Ezs Eg IDAC_ICC IDAC_ICC Integral non linearity Differential non linearity Zero scale error Gain error DAC current low speed mode[28] DAC current high speed mode[28] Uncompensated Temperature compensated Code = 0 Code = 0 Code = 255, RL 600 Code = 255, RL 600 RL 600 , CL=15 pF RL 600 , CL=15 pF - - - - - - - - - - - 2.040 2.040 255 31.875 - - 0 - - - - - - - -
1 0.5 1
Description
Conditions
Min -
Typ 8
Max -
Units
mA mA A A LSB LSB LSB % % A A
3.5 TBD 100 500
Table 11-26. IDAC (Current Digital-to-Analog Converter) AC Specifications Parameter FDAC Description Update rate Settling time to 0.5LSB Fast mode Slow mode Conditions Full scale transition, 600 load, CL = 15 pF Independent of IDAC range setting (IOUT) Independent of IDAC range setting (IOUT) Min - Typ - Max 8 Units Msps
TSETTLE
- -
- -
100 1000
ns ns
Note 28. Based on device characterization (Not production tested).
Document Number: 001-55035 Rev. *G
Page 72 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
11.5.7 VDAC Table 11-27. VDAC (Voltage Digital-to-Analog Converter) DC Specifications Parameter Resolution Output resistance[29] ROUT High Low Output voltage range[29] VOUT INL DNL Ezs Eg VDAC_ICC VDAC_ICC High Low Integral non linearity Differential non linearity Zero scale error Gain error DAC current low speed mode[29] Uncompensated Temperature compensated Code = 0 Code = 0 DAC current high speed mode[29] Code = 255, VDDA > 5 V Code = 255 CL=15 pF CL=15 pF - - - - - - - - - 4 1 - - - - - - - - -
1 1 1
Description
Conditions
Min -
Typ 8 16 4
Max - - -
Units
VOUT = 4 V VOUT = 1 V
- -
k k V V LSB LSB LSB % % A A
3 TBD 100 500
Table 11-28. VDAC (Voltage Digital-to-Analog Converter) AC Specifications Parameter FDAC Update Description rate[29] 0.5LSB[29] 1 V mode 4 V mode Full scale transition, CL = 15 pF VOUT = 4 V VOUT = 1 V - - - - 4000 1000 ns ns Update rate[29] Settling time to TSETTLE High[29] Low[29] 11.5.8 Discrete Time Mixer The discrete time mixer is used for modulating (shifting signals in frequency down) where the output frequency of the mixer is equal to the difference of the input frequency and the local oscillator frequency. The discrete time mixer is created using a SC/CT analog block; see the Mixer component datasheet in PSoC Creator for full AC/DC specifications, and APIs and example code. Table 11-29. Discrete Time Mixer DC Specifications Parameter Description Conditions 4 MHz clock rate Input voltage[30] Input offset voltage Quiescent current Table 11-30. Discrete Time Mixer AC Specifications Parameter LO Description Local oscillator frequency[29] Input signal frequency for down mixing[29] Conditions Min 0 0 Typ - - Max 4 14 Units MHz MHz Min - - VSSA - - Typ. 10 30 - - 0.9 Max - - VDDA 10 2 Units V V V mV mA Analog input noise injection (RMS) 1 MHz clock rate Conditions Min - - Typ - - Max 1 250 Units Msps Ksps
Notes 29. Based on device characterization (Not production tested). 30. Bandwidth is guaranteed for input common mode between 0.3 V and VDDA-1.2 V and for output that is between 0.05 V and VDDA-0.05 V.
Document Number: 001-55035 Rev. *G
Page 73 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
11.5.9 Continuous Time Mixer The continuous time mixer is used for modulating (shift) frequencies up or down, to a limit of 1.0 MHz. The continuous time mixer is created using a SC/CT analog block; see the Mixer component datasheet in PSoC Creator for full AC/DC specifications, and APIs and example code. Table 11-31. Continuous Time Mixer DC Specifications Parameter Description Input voltage[31] Input offset voltage Quiescent current Table 11-32. Continuous Time Mixer AC Specifications Parameter LO Description Local oscillator frequency[32] Input signal frequency[32] Conditions Min - - Typ - - Max 1 1 Units MHz MHz Conditions Min - VSSA - - Typ - - - 0.9 Max 10 VDDA 10 2 Units V V mV mA Analog input noise injection (RMS) No input signal
11.5.10 Transimpedance Amplifier The TIA is created using a SC/CT analog block; see the TIA component datasheet in PSoC Creator for full AC/DC specifications, and APIs and example code. Table 11-33. Transimpedance Amplifier (TIA) DC Specifications Parameter VIOFF Description Input offset voltage Conversion resistance[33] R = 20K R = 30K R = 40K Rconv R = 80K R = 120K R = 250K R= 500K R = 1M Quiescent current Table 11-34. Transimpedance Amplifier (TIA) AC Specifications Parameter R = 20K R = 120K R = 1M Input bandwidth (3 dB) - 40 pF load R = 20K R = 120K R = 1M 1500 300 46 - - - - - - kHz kHz kHz Description Input bandwidth (-3 dB) - 20 pF load[31] 1800 330 47 - - - - - - kHz kHz kHz Conditions Min Typ Max Units 40 pF load 40 pF load 40 pF load 40 pF load 40 pF load 40 pF load 40 pF load 40 pF load -20 -20 -20 -20 -20 -20 -20 -20 - - - - - - - - - 900 +30 +30 +30 +30 +30 +30 +30 +30 - % % % % % % % % A Conditions Min - Typ - Max 10 Units mV
Notes 31. Bandwidth is guaranteed for input common mode between 0.3 V and VDDA-1.2 V and for output that is between 0.05 V and VDDA-0.05 V. 32. Based on device characterization (Not production tested). 33. Conversion resistance values are not calibrated. Calibrated values and details about calibration are provided in PSoC Creator component datasheets. External precision
Document Number: 001-55035 Rev. *G
Page 74 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
11.5.11 Programmable Gain Amplifier The PGA is created using a SC/CT analog block; see the PGA component datasheet in PSoC Creator for full AC/DC specifications, and APIs and example code. Table 11-35. PGA DC Specifications Parameter VOS Description Input offset voltage[34] drift[34] ratio[34] 100 kHz 1 MHz Zin Ge1 Ge2 Ge4 Ge8 Ge16 Ge32 Ge50 VONL VOH, VOL Input impedance[34] For non inverting inputs Non inverting mode, reference = VSSA Rin of 40 K Rin of 40 K Rin of 40 K Rin of 40 K Rin of 40 K Rin of 40 K Rin of 40 K - - - - - - VSSA + 0.15 - - - - - - - - - - -
0.15 1 1.03 1.23 2.5 5 5
Conditions
Min - - - 69 38 35
Typ - 30 - - - -
Max 10 250 - - -
Units mV V/C A dB dB M % % % % % % % % of FSR V mA
DeltaV/DeltaTa Input offset voltage PSRR
Output current source capability[34] Drive setting 3, VDDA = 1.71 V Power supply rejection
Gain Error[34] Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 Gain = 32 Gain = 50 DC output non linearity G = 1[34] Output voltage swing Quiescent current[15] Table 11-36. PGA AC Specifications Parameter BW1 BW24 BW48 Gain = 1 Gain = 24 Gain = 48 Slew Rate[34] SR1 SR24 SR48 eni1 eni24 eni48 Gain = 1 Gain = 24 Gain = 48 Input Noise Voltage Density[34] Gain = 1 Gain = 24 Gain = 48 Description -3 db Bandwidth[34]
0.01 VDDA - 0.15 1.65
Conditions Noninverting mode, 300 mV VIN VDDA - 1.2 V, Cl 25 pF Noninverting mode, 300 mV VIN VDDA - 1.2 V, Cl 25 pF Noninverting mode, 300 mV VIN VDDA - 1.2 V, Cl 25 pF VDDA = 1.71 V 5% to 90% FS output RC limited RC limited 10 kHz 10 kHz 10 kHz
Min 7 360 215
Typ - - -
Max - - -
Units MHz kHz kHz
3 0.5 0.5 - - -
- - - 38 38 38
- - - - - -
V/s V/s V/s nV/sqrtHz nV/sqrtHz nV/sqrtHz
Note 34. Based on device characterization (Not production tested).
Document Number: 001-55035 Rev. *G
Page 75 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
11.5.12 Unity Gain Buffer The unity gain buffer is created using a SC/CT analog block. See the Unity Gain Buffer component datasheet in PSoC Creator for full AC/DC specifications, and APIs and example code. Table 11-37. Unity Gain Buffer DC Specifications Parameter VOS Input offset Description voltage[35] Offset voltage drift Input voltage range VOH, VOL Output voltage range Output current source capability[35] Drive setting 3, VDDA = 1.71 V Quiescent current Table 11-38. Unity Gain Buffer AC Specifications Parameter Description Bandwidth[35, 36] Slew rate[35] Input noise spectral density[35] 11.5.13 Temperature Sensor Table 11-39. Temperature Sensor Specifications Parameter Description Temp sensor accuracy Conditions Range: -40 C to +85 C Min - Typ 5 Max - Units C Conditions Noninverting mode, 300 mV VIN VDDA - 1.2 V, Cl 25 pF VDDA = 1.71 V 5% to 90% FS output, CL = 50 pF Min 7 3 - Typ - - 38 Max - - - Units MHz V/s nV/sqrtHz Conditions Min - - VSSA VSSA + 0.15 - - Typ - - - - - 900 Max 10 30 VDDA VDDA - 0.15 250 - Units mV v/C V V A A
11.5.14 LCD Direct Drive Table 11-40. LCD Direct Drive DC Specifications Parameter ICC VBIAS Description LCD operating current Conditions 16x4 segment display at 50 Hz [37]. Min - 2 Typ 19 - Max - 5.5 Units A V
LCD bias range (VBIAS refers to the VDDA 3 V and VDDA VBIAS main output voltage(V0) of LCD DAC) LCD bias step size LCD capacitance per segment/common driver Long term segment offset IOUT (Output drive current per segment driver) Strong drive ICC per segment driver Strong drive Output current in strong drive mode for VDDIO = 5.5 V VDDA 3 V and VDDA VBIAS Drivers may be combined.
- - - 528
9.1 x VDDA 500 - -
- 5000 10 655
mV pF mV A
220
260
300
A
Notes 35. Based on device characterization (Not production tested). 36. Bandwidth is guaranteed for input common mode between 0.3 V and VDDA-1.2 V and for output that is between 0.05 V and VDDA-0.05 V. 37. This is the LCD system operating current when there is no LCD display. Connecting an actual LCD display increases the current consumption based on the size of the LCD glass.
Document Number: 001-55035 Rev. *G
Page 76 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Table 11-40. LCD Direct Drive DC Specifications (continued) Parameter Description Weak drive Weak drive 2 No drive Static (1 common) IccLCD IccLCD LCD system operating current VBIAS = 5 V Number of LCD pins: 33 (32x1) Number of segments: 32[38] VBIAS = 3 V Number of LCD pins: 33 (32x1) Number of segments: 32[38] VBIAS = 5 V Number of LCD pins: 36 (32x4) Number of segments: 128[38] VBIAS = 3 V Number of LCD pins: 36 (32x4) Number of segments: 128[38] VBIAS = 5 V Number of LCD pins: 48 (32x16) Number of segments: 512[38] VBIAS = 3 V Number of LCD pins: 48 (32x16) Number of segments: 512[38] - 12 - A Conditions Min - - - Typ 11 22 <25 Max - - - Units A A nA
LCD system operating current
-
10
-
A
1/4 duty (4 commons) IccLCD IccLCD LCD system operating current - 24 - A
LCD system operating current
-
21
-
A
1/16 duty (16 commons) IccLCD IccLCD LCD system operating current - 93 - A
LCD system operating current
-
83
-
A
Table 11-41. LCD Direct Drive AC Specifications Parameter fLCD Description LCD frame rate Conditions Min 10 Typ 50 Max 150 Units Hz
Note 38. Additional conditions: All segments on; 2000 pF glass capacitance; Type A waveform; 32 Hz LCD refresh rate; Operating temperature = 25 C; Boost converter not used.
Document Number: 001-55035 Rev. *G
Page 77 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
11.6 Digital Peripherals
Specifications are valid for -40 C TA 85 C and TJ 100 C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. 11.6.1 Timer Table 11-42. Timer DC Specifications Parameter Description Block current consumption 3 MHz 12 MHz 48 MHz 67 MHz 80 MHz Table 11-43. Timer AC Specifications Parameter Description Operating frequency Capture pulse width (Internal) Capture pulse width (external) Timer resolution Enable pulse width Enable pulse width (external) Reset pulse width Reset pulse width (external) 11.6.2 Counter Table 11-44. Counter DC Specifications Parameter Description Block current consumption 3 MHz 12 MHz 48 MHz 67 MHz 80 MHz Table 11-45. Counter AC Specifications Parameter Description Operating frequency Capture pulse Resolution Pulse width Pulse width (external) Enable pulse width Enable pulse width (external) Reset pulse width Reset pulse width (external)
Document Number: 001-55035 Rev. *G
Conditions 16-bit timer, at listed input clock frequency
Min - - - - - -
Typ - 8 30 120 165 195
Max - - - - - -
Units A A A A A A
Conditions
Min DC 13 30 13 13 30 13 30
Typ - - - - - - - -
Max 80 - - - - - - -
Units MHz ns ns ns ns ns ns ns
Conditions 16-bit counter, at listed input clock frequency
Min - - - - - -
Typ - 8 30 120 165 195
Max - - - - - -
Units A A A A A A
Conditions
Min DC 13 13 13 30 13 30 13 30
Typ - - - - - - - - -
Max 80 - - - - - - - -
Units MHz ns ns ns ns ns ns ns ns
Page 78 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
11.6.3 Pulse Width Modulation Table 11-46. PWM DC Specifications Parameter Description Block current consumption 3 MHz 12 MHz 48 MHz 67 MHz 80 MHz Table 11-47. PWM AC Specifications Parameter Pulse width Pulse width (external) Kill pulse width Kill pulse width (external) Enable pulse width Enable pulse width (external) Reset pulse width Reset pulse width (external) 11.6.4 I2C Table 11-48. Fixed I2C DC Specifications Parameter Description Block current consumption Conditions Enabled, configured for 100 kbps Enabled, configured for 400 kbps Wake from sleep mode Table 11-49. Fixed I2C AC Specifications Parameter Bit rate 11.6.5 Controller Area Network[39] Table 11-50. CAN DC Specifications Parameter Description Block current consumption 500 kbps 1 Mbps Table 11-51. CAN AC Specifications Parameter Bit rate
Note 39. Refer to ISO 11898 specification for details.
Conditions 16-bit PWM, at listed input clock frequency
Min - - - - - -
Typ - 8 30 120 165 195
Max - - - - - -
Units A A A A A A
Description Operating frequency
Conditions
Min DC 13 30 13 30 13 30 13 30
Typ - - - - - - - - -
Max 80 - - - - - - - -
Units MHz ns ns ns ns ns ns ns ns
Min - - -
Typ - - -
Max 64 74 TBD
Units A A A
Description
Conditions
Min -
Typ -
Max 1
Units Mbps
Conditions
Min - -
Typ - -
Max 285 330
Units A A
Description
Conditions Minimum 8 MHz clock
Min -
Typ -
Max 1
Units Mbit
Document Number: 001-55035 Rev. *G
Page 79 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
11.6.6 USB Table 11-52. USB DC Specifications Parameter Description Operating current 11.6.7 Universal Digital Blocks (UDBs) PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM, AND, OR, and so on) that are mapped to the UDB array. See the component datasheets in PSoC Creator for full AC/DC specifications, APIs, and example code. Table 11-53. UDB AC Specifications Parameter Datapath Performance FMAX_TIMER Maximum frequency of 16-bit timer in a UDB pair FMAX_ADDER Maximum frequency of 16-bit adder in a UDB pair FMAX_CRC Maximum frequency of 16-bit CRC/PRS in a UDB pair Maximum frequency of a two-pass PLD function in a UDB pair Propagation delay for clock in to data 25 C operating temperature out, see Figure 11-1. Propagation delay for clock in to data Worst-case placement, routing, out, see Figure 11-1. and pin selection Figure 11-1. Clock to Output Performance - - - - - - 80 80 80 MHz MHz MHz Description Conditions Min Typ Max Units Conditions USB enabled bus idle Min - Typ 0.68 Max - Units mA
PLD Performance FMAX_PLD - - 80 MHz
Clock to Output Performance tCLK_OUT tCLK_OUT - - TBD TBD TBD TBD ns ns
Document Number: 001-55035 Rev. *G
Page 80 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
11.7 Memory
Specifications are valid for -40 C TA 85 C and TJ 100 C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. 11.7.1 Flash Table 11-54. Flash DC Specifications Parameter Description Erase and program voltage Table 11-55. Flash AC Specifications Parameter TWRITE TERASE TBULK Description Row write time (erase + program) Row erase time Row program time Bulk erase time (256 KB) Sector erase time (16 KB) Total device program time (including JTAG, and so on) Flash endurance Conditions Min - - - - - - 100 k Typ - - - - - - - Max 15 10 5 80 15 5 - Units ms ms ms ms ms seconds program/ erase cycles years VDDD pin Conditions Min 1.71 Typ - Max 5.5 Units V
Flash data retention time
Retention period measured from last erase cycle
20
-
-
11.7.2 EEPROM Table 11-56. EEPROM DC Specifications Parameter Description Erase and program voltage Table 11-57. EEPROM AC Specifications Parameter TWRITE Description Single byte erase/write cycle time EEPROM endurance Conditions Min - 1M Typ 2 - Max 15 - Units ms program/ erase cycles years Conditions Min 1.71 Typ - Max 5.5 Units V
EEPROM data retention time
Retention period measured from last erase cycle (up to 100 K cycles)
20
-
-
11.7.3 Nonvolatile Latches (NVL) Table 11-58. NVL DC Specifications Parameter Description Erase and program voltage VDDD pin Conditions Min 1.71 Typ - Max 5.5 Units V
Document Number: 001-55035 Rev. *G
Page 81 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Table 11-59. NVL AC Specifications Parameter Description NVL endurance Conditions Programmed at 25 C Min 1K Typ - Max - Units program/ erase cycles program/ erase cycles years years
Programmed at 0 C to 70 C
100
-
-
NVL data retention time
Programmed at 25 C Programmed at 0 C to 70 C
20 20
- -
- -
11.7.4 SRAM Table 11-60. SRAM DC Specifications Parameter VSRAM Description SRAM retention voltage Conditions Min 1.2 Typ - Max - Units V
Table 11-61. SRAM AC Specifications Parameter FSRAM Description SRAM operating frequency Conditions Min DC Typ - Max 80 Units MHz
11.7.5 External Memory Interface Figure 11-2. Asynchronous Read Cycle Timing
Tcel
EM_CEn
Taddrv Taddrh
EM_Addr
Toev
Address
Toel Toeh
EM_OEn
EM_WEn
Tdoesu Tdcesu Tdoeh Tdceh
EM_Data
Data
Table 11-62. Asynchronous Read Cycle Specifications Parameter T Tcel Taddrv Taddrh Toev Description EMIF clock period EM_CEn low time EM_CEn low to EM_Addr valid Address hold time after EM_OEn high EM_CEn low to EM_OEn low Conditions Min 30.3 2xT-1 - 2 -5 Typ - - - - - Max - 2xT+2 5 - 5 Units ns ns ns ns ns
Document Number: 001-55035 Rev. *G
Page 82 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Table 11-62. Asynchronous Read Cycle Specifications (continued) Parameter Toel Toeh Tdoesu Tdcesu Tdoeh Tdceh Description EM_OEn low time EM_OEn high to EM_CEn high hold time Data to EM_OEn high setup time Data to EM_CEn high setup time Data hold time after EM_OEn high Data hold time after EM_CEn high Conditions Min 2xT-1 -5 T + 20 T + 20 3 3 Typ - - - - - - Max 2xT+2 5 - - - - Units ns ns ns ns ns ns
Figure 11-3. Asynchronous Write Cycle Timing
Taddrv Taddrh
EM_ Addr
Address
Tcel
EM_ CEn
EM_ OEn
Twev Twel Tweh
EM_WEn
Tdweh
Tdcev
EM_ Data
Data
Table 11-63. Asynchronous Write Cycle Specifications Parameter T Taddrv Taddrh Tcel Twev Twel Tweh Tdcev Tdweh Description EMIF clock period EM_CEn low to EM_Addr valid Address hold time after EM_WEn high EM_CEn low time EM_CEn low to EM_WEn low EM_WEn low time EM_WEn high to EM_CEn high hold time EM_CEn low to data valid Data hold time after EM_WEn high Conditions Min 30.3 - T+2 2xT-1 -5 T-1 T - T Typ - - - - - - - - - Max - 5 - 2xT+2 5 T+2 - 7 - Units ns ns ns ns ns ns ns ns ns
Document Number: 001-55035 Rev. *G
Page 83 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Figure 11-4. Synchronous Read Cycle Timing
Tcp
EM_ Clock
Tceld Tcehd
EM_ CEn
Taddrv Taddriv
EM_ Addr
Toeld Toehd
Address
EM_ OEn
Tds Tdh
EM_ Data
Tadscld
Data
Tadschd
EM_ ADSCn
Table 11-64. Synchronous Read Cycle Specifications Parameter T Tcp Tceld Tcehd Taddrv Taddriv Toeld Toehd Tds Tdh Tadscld Tadschd Description EMIF clock period EM_clock period EM_clock low to EM_CEn low EM_clock high to EM_CEn high EM_clock low to EM_Addr valid EM_clock high to EM_Addr invalid EM_clock low to EM_OEn low EM_clock high to EM_OEn high Data valid before EM_Clock high Data valid after EM_Clock high EM_clock low to EM_ADSCn low EM_clock high to EM_ADSCn high Conditions Min 30.3 30.3 - T/2 - 2 - T/2 - 2 - T+2 20 2 - T/2 - 2 Typ - - - - - - - - - - - - Max - - 5 - 5 - 5 - - - 5 - Units ns ns ns ns ns ns ns ns ns ns ns ns
Document Number: 001-55035 Rev. *G
Page 84 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Figure 11-5. Synchronous Write Cycle Timing
Tcp
EM_ Clock
Tceld Tcehd
EM_ CEn
Taddrv Taddriv
EM_ Addr
Tweld Twehd
Address
EM_ WEn
Tds
EM_ Data
Tadscld
Data
Tadschd
EM_ ADSCn
Table 11-65. Synchronous Write Cycle Specifications Parameter T Tcp Tceld Tcehd Taddrv Taddriv Tweld Twehd Tds Tadscld Tadschd Description EMIF clock period EM_clock period EM_clock low to EM_CEn low EM_clock high to EM_CEn high EM_clock low to EM_Addr valid EM_clock high to EM_Addr invalid EM_clock low to EM_WEn low EM_clock high to EM_WEn high Data valid after EM_Clock low EM_clock low to EM_ADSCn low EM_clock high to EM_ADSCn high Conditions Min 30.3 30.3 - T/2 - 2 - T/2 - 2 - T/2 - 2 - - T/2 - 2 Typ - - - - - - - - - - - Max - - 5 - 5 - 5 - 5 5 - Units ns ns ns ns ns ns ns ns ns ns ns
Document Number: 001-55035 Rev. *G
Page 85 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
11.8 PSoC System Resources
Specifications are valid for -40 C TA 85 C and TJ 100 C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. 11.8.1 POR with Brown Out For brown out detect in regulated mode, VDDD and VDDA must be 2.0 V. Brown out detect is available in externally regulated mode. Table 11-66. Precise Power On Reset (PRES) with Brown Out DC Specifications Parameter PRESR PRESF Description Precise POR (PPOR) Rising trip voltage Falling trip voltage 1.66 1.63 - - 1.73 1.70 V V Conditions Min Typ Max Units
Table 11-67. Power On Reset (POR) with Brown Out AC Specifications Parameter Description VDDD/VDDA drop rate 11.8.2 Voltage Monitors Table 11-68. Voltage Monitors DC Specifications Parameter LVI Trip voltage LVI_A/D_SEL[3:0] = 0000b LVI_A/D_SEL[3:0] = 0001b LVI_A/D_SEL[3:0] = 0010b LVI_A/D_SEL[3:0] = 0011b LVI_A/D_SEL[3:0] = 0100b LVI_A/D_SEL[3:0] = 0101b LVI_A/D_SEL[3:0] = 0110b LVI_A/D_SEL[3:0] = 0111b LVI_A/D_SEL[3:0] = 1000b LVI_A/D_SEL[3:0] = 1001b LVI_A/D_SEL[3:0] = 1010b LVI_A/D_SEL[3:0] = 1011b LVI_A/D_SEL[3:0] = 1100b LVI_A/D_SEL[3:0] = 1101b LVI_A/D_SEL[3:0] = 1110b LVI_A/D_SEL[3:0] = 1111b HVI Trip voltage Description Conditions Min - 1.68 1.91 2.16 2.40 2.65 2.90 3.14 3.39 3.63 3.88 4.12 4.36 4.61 4.88 5.11 5.36 5.630 Typ - 1.73 1.95 2.21 2.45 2.71 2.96 3.21 3.46 3.71 3.96 4.21 4.45 4.70 4.98 5.22 5.47 5.745 Max - 1.77 1.99 2.25 2.50 2.76 3.01 3.27 3.53 3.78 4.03 4.29 4.54 4.79 5.08 5.32 5.57 5.860 V V V V V V V V V V V V V V V V V Units Conditions Sleep mode Min - - Typ - 5 Max 250 TBD Units ns V/s PRES_TR Response time
Table 11-69. Voltage Monitors AC Specifications Parameter Description Response time Conditions Min - Typ - Max 500 Units ns
Document Number: 001-55035 Rev. *G
Page 86 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
11.8.3 Interrupt Controller Table 11-70. Interrupt Controller AC Specifications Parameter Description Conditions Min - Typ - Max 20 Units Tcy CPU Delay from interrupt signal input to ISR Includes worse case completion of code execution from main line code longest instruction DIV with 6 cycles Delay from interrupt signal input to ISR Includes worse case completion of code execution from ISR code longest instruction DIV with 6 cycles 11.8.4 JTAG Interface Table 11-71. JTAG Interface AC Specifications[40] Parameter f_TCK T_TDI_setup T_TDI_hold T_TDO_valid T_TDO_hold Description TCK frequency TDI, TMS setup before TCK high TDI, TMS hold after TCK high TCK low to TDO valid TDO hold after TCK high TCK to device outputs valid 11.8.5 SWD Interface Table 11-72. SWD Interface AC Specifications[40] Parameter f_SWDCK Description SWDCLK frequency Conditions 3.3 V VDDD 5 V 1.71 V VDDD < 3.3 V 1.71 V VDDD < 3.3 V, SWD over USBIO pins T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK T_SWDI_hold SWDIO input hold after SWDCK high T = 1/f_SWDCK T = 1/f_SWDCK T_SWDO_valid SWDCK low to SWDIO output valid Min - - - T/4 T/4 2T/5 T/4 Typ - - - - - - - Max 14[42] 7[42] 5.5[42] - - - - Units MHz MHz MHz T = 1/f_TCK T = 1/f_TCK T = 1/f_TCK Conditions 3.3 V VDDD 5 V 1.71 V VDDD < 3.3 V Min - - 0 T/4 2T/5 T/4 - Typ - - - - - - - Max 14[41] 7[41] - - - - TBD ns Units MHz MHz ns
-
-
20
Tcy CPU
T_SWDO_hold SWDIO output hold after SWDCK high T = 1/f_SWDCK 11.8.6 TPIU Interface Table 11-73. TPIU Interface AC Specifications[40] Parameter SWV bit rate Description TRACEPORT (TRACECLK) frequency Conditions
Min - -
Typ - -
Max 33[43] 33[43]
Units MHz Mbit
Notes 40. Based on device characterization (Not production tested). 41. f_TCK must also be no more than 1/3 CPU clock frequency. 42. f_SWDCK must also be no more than 1/3 CPU clock frequency. 43. TRACEPORT signal frequency and bit rate are limited by GPIO output frequency. See "GPIO" on page 63.for AC Specifications.
Document Number: 001-55035 Rev. *G
Page 87 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
11.9 Clocking
Specifications are valid for -40 C TA 85 C and TJ 100 C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. 11.9.1 32 kHz External Crystal Table 11-74. 32 kHz External Crystal DC Specifications[44] Parameter Description Operating current ICC CL External crystal capacitance DL Drive level Conditions Low power mode Min - - - Typ - 6 - Max 0.25 - 1 Units A pF W
Table 11-75. 32 kHz External Crystal AC Specifications Parameter Description F Frequency DC Output duty cycle[44] Startup time TON 11.9.2 Internal Main Oscillator) Table 11-76. IMO DC Specifications Parameter Description Supply current 74.7 MHz 48 MHz 24 MHz - USB mode 24 MHz - non USB mode 12 MHz 6 MHz 3 MHz Conditions Min - - - - - - - Typ - - - - - - - Max 600 500 500 300 200 180 150 Units A A A A A A A Conditions Min - 20 - Typ 32.768 50 1 Max - 80 - Units kHz % s
High power mode
With oscillator locking to USB bus
Table 11-77. IMO AC Specifications
Parameter Description Conditions IMO frequency stability (with factory trim) 74.7 MHz 48 MHz 24 MHz - Non USB mode 24 MHz - USB mode With oscillator locking to USB bus 12 MHz 6 MHz 3 MHz From enable (during normal system Startup time[44] operation) or wakeup from low power state [44] Jitter (peak to peak) F = 24 MHz F = 3 MHz Jitter (long term)[44] F = 24 MHz F = 3 MHz Min -7 -5 -4 -0.25 -3 -2 -1 - Typ - - - - - - - - Max 7 5 4 0.25 3 2 1 12 Units % % % % % % % s
FIMO
Jp-p
- - - -
0.9 1.6 0.9 12
- - - -
ns ns ns ns
Jperiod
Note 44. Based on device characterization (Not production tested).
Document Number: 001-55035 Rev. *G
Page 88 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
11.9.3 Internal Low Speed Oscillator Table 11-78. ILO DC Specifications Parameter ICC Leakage current Table 11-79. ILO AC Specifications Parameter Startup time Startup time Startup time Duty cycle ILO frequencies (trimmed) 100 kHz FILO 1 kHz ILO frequencies (untrimmed) 100 kHz 1 kHz 11.9.4 External Crystal Oscillator Table 11-80. ECO AC Specifications Parameter F DC Duty cycle[45] Description Crystal frequency range Conditions Min 4 40 Typ - 50 Max 33 60 Units MHz % 30 0.3 100 1 300 3.5 kHz kHz 45 0.5 100 1 200 2 kHz kHz Description Conditions Turbo mode Non turbo mode, pd_mode = 0 Non turbo mode, pd_mode = 1 Min - - - 47 Typ - - - 50 Max 2 2 15 53 Units ms ms ms % Description Operating current Conditions FOUT = 1 kHz FOUT = 33 kHz FOUT = 100 kHz Power down mode Min - - - - Typ 0.3 1.0 1.0 2.0 Max 1.7 2.6 2.6 15 Units A A A nA
11.9.5 External Clock Reference Table 11-81. External Clock Reference AC Specifications[45] Parameter Description External frequency range Input duty cycle range Input edge rate Measured at VDDIO/2 VIL to VIH Conditions Min 0 30 0.1 Typ - 50 - Max 33 70 - Units MHz % V/ns
Note 45. Based on device characterization (Not production tested).
Document Number: 001-55035 Rev. *G
Page 89 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
11.9.6 Phase-Locked Loop Table 11-82. PLL DC Specifications Parameter IDD Description PLL operating current Conditions In = 3 MHz, Out = 80 MHz In = 3 MHz, Out = 24 MHz Table 11-83. PLL AC Specifications Parameter Fpllin Fpllout PLL input Description frequency[46] Output of prescaler PLL intermediate frequency[47] PLL output frequency[46] Lock time at startup Jperiod-rms Jitter (rms)[48] All PLL output frequencies PLL output duty cycle Conditions Min 1 1 24 - - 45 Typ - - - - - - Max 48 3 67 250 250 55 Units MHz MHz MHz s ps % Min - - Typ 400 200 Max - - Units A A
Notes 46. This specification is guaranteed by testing the PLL across the specified range using the IMO as the source for the PLL. 47. PLL input divider, Q, must be set so that the input frequency is divided down to the intermediate frequency range. Value for Q ranges from 1 to 16. 48. Based on device characterization (Not production tested).
Document Number: 001-55035 Rev. *G
Page 90 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
12. Ordering Information
In addition to the features listed in Table 12-1, every CY8C53 device includes: up to 128 KB flash, 32 KB SRAM, 2 KB EEPROM, a precision on-chip voltage reference, precision oscillators, flash, ECC, DMA, a fixed function I2C, JTAG/SWD programming and debug, external memory interface, and more. In addition to these features, the flexible UDBs and analog subsection support a wide range of peripherals. To assist you in selecting the ideal part, PSoC Creator makes a part recommendation after you choose the components required by your application. All CY8C53 derivatives incorporate device and flash security in user-selectable security levels; see the TRM for details. Table 12-1. CY8C53 Family with ARM Cortex-M3 CPU
MCU Core Analog SC/CT Analog Blocks[49]
Digital
I/O[51]
LCD Segment Drive
16-bit Timer/PWM
CPU Speed (MHz)
EEPROM (KB)
Comparators
Part Number
Package CAN 2.0b Total I/O FS USB
JTAG ID[52]
SRAM (KB)
Flash (KB)
DFB CapSense
UDBs[50]
Opamps
32 KB Flash CY8C5385AXI-015 CY8C5385LTI-034 CY8C5385PVI-109 CY8C5385AXI-043 CY8C5385LTI-104 CY8C5385PVI-042 CY8C5385AXI-025 CY8C5385PVI-080 CY8C5385AXI-096 CY8C5385PVI-010 64 KB Flash CY8C5386AXI-076 CY8C5386LTI-005 CY8C5386PVI-070 CY8C5386AXI-001 CY8C5386LTI-053 CY8C5386PVI-057 CY8C5386AXI-081 CY8C5386PVI-040 CY8C5386AXI-105 CY8C5386PVI-098 128 KB Flash CY8C5387AXI-099 CY8C5387LTI-075 CY8C5387PVI-031 CY8C5387AXI-108 CY8C5387LTI-003 80 80 80 80 80 128 32 128 32 128 32 128 32 128 32 2 2 2 2 2
1 x 12-bit SAR 2 1 x 12-bit SAR 2
80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80
32 32 32 32 32 32 32 32 32 32 64 64 64 64 64 64 64 64 64 64
8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1 x 12-bit SAR 2 1 x 12-bit SAR 2
4 2 2 - 20 4 2 2 - 20 - 20 4 2 2 - 20 4 2 2 - 20 - 20 - 20 - 20 4 2 2 - 20 4 2 2 - 20
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
-- --

70 46 29 72 48 31 70 29 72 31 70 46 29 72 48 31 70 29 72 31 70 46 29 72 48
62 38 25 62 38 25 62 25 62 25 62 38 25 62 38 25 62 25 62 25 62 38 25 62 38
8 8 4 8 8 4 8 4 8 4 8 8 4 8 8 4 8 4 8 4 8 8 4 8 8
USBIO 0 0 0 2 2 2 0 0 2 2 0 0 0 2 2 2 0 0 2 2 0 0 0 2 2 100-pin TQFP 0x0E10F069 68-pin QFN 48-SSOP 68-pin QFN 48-SSOP 48-SSOP 48-SSOP 0x0E122069 0x0E16D069 0x0E168069 0x0E12A069 0x0E150069 0x0E10A069 100-pin TQFP 0x0E12B069 100-pin TQFP 0x0E119069 100-pin TQFP 0x0E160069 100-pin TQFP 0x0E14C069 68-pin QFN 48-SSOP 68-pin QFN 48-SSOP 48-SSOP 48-SSOP 0x0E105069 0x0E146069 0x0E135069 0x0E139069 0x0E128069 0x0E162069 100-pin TQFP 0x0E101069 100-pin TQFP 0x0E151069 100-pin TQFP 0x0E169069 100-pin TQFP 0x0E163069 68-pin QFN 48-SSOP 68-pin QFN 0x0E14B069 0x0E11F069 0x0E103069 100-pin TQFP 0x0E16C069
GPIO
ADC
DAC
1x12-bit SAR
2422
-
1 x 12-bit SAR 2 1 x 12-bit SAR 2
- -

1x12-bit SAR 1x12-bit SAR 1x12-bit SAR
2422 2422 2422
1 x 12-bit SAR 2 1 x 12-bit SAR 2
-

1 x 12-bit SAR 2 1 x 12-bit SAR 2
4 2 2 - 24 4 2 2 - 24 - 24 4 2 2 - 24 4 2 2 - 24 - 24 - 24 - 24 4 2 2 - 24 4 2 2 - 24
-- --

1x12-bit SAR
2422
-
1 x 12-bit SAR 2 1 x 12-bit SAR 2
- -

1x12-bit SAR 1x12-bit SAR 1x12-bit SAR
2422 2422 2422
1 x 12-bit SAR 2 1 x 12-bit SAR 2
-

4 2 2 - 24 4 2 2 - 24 - 24 4 2 2 - 24 4 2 2 - 24
-- --

1x12-bit SAR
2422
-
1 x 12-bit SAR 2 1 x 12-bit SAR 2
- -
Notes 49. Analog blocks support a wide variety of functionality including TIA, PGA, and mixers. See Example Peripherals on page 34 for more information on how analog blocks can be used. 50. UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or multiple UDBs. Multiple functions can share a single UDB. See Example Peripherals on page 34 for more information on how UDBs can be used. 51. The I/O Count includes all types of digital I/O: GPIO, SIO, and the two USB I/O. See I/O System and Routing on page 28 for details on the functionality of each of these types of I/O. 52. The JTAG ID has three major fields. The most significant nibble (left digit) is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID.
Document Number: 001-55035 Rev. *G
SIO
Page 91 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Table 12-1. CY8C53 Family with ARM Cortex-M3 CPU (continued)
CY8C5387PVI-036 CY8C5387AXI-023 CY8C5387PVI-045 CY8C5387AXI-083 CY8C5387PVI-072 256 KB Flash CY8C5388AXI-008 CY8C5388LTI-032 CY8C5388PVI-055 CY8C5388AXI-106 CY8C5388LTI-026 CY8C5388PVI-014 CY8C5388AXI-088 CY8C5388PVI-016 CY8C5388AXI-035 CY8C5388PVI-027 80 80 80 80 80 80 80 80 80 80 256 64 256 64 256 64 256 64 256 64 256 64 256 64 256 64 256 64 256 64 2 2 2 2 2 2 2 2 2 2
1 x 12-bit SAR 2 1 x 12-bit SAR 2
80 80 80 80 80
128 32 128 32 128 32 128 32 128 32
2 2 2 2 2

1x12-bit SAR 1x12-bit SAR 1x12-bit SAR
2422 2422 2422
- 24 - 24 - 24
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

31 70 29 72 31 70 46 29 72 48 31 70 29 72 31
25 62 25 62 25 62 38 25 62 38 25 62 25 62 25
4 8 4 8 4 8 8 4 8 8 4 8 4 8 4
2 0 0 2 2 0 0 0 2 2 2 0 0 2 2
48-SSOP 48-SSOP 48-SSOP
0x0E124069 0x0E12D069 0x0E148069
1 x 12-bit SAR 2 1 x 12-bit SAR 2
4 2 2 - 24 4 2 2 - 24
-

100-pin TQFP 0x0E117069 100-pin TQFP 0x0E153069
4 2 2 - 24 4 2 2 - 24 - 24 4 2 2 - 24 4 2 2 - 24 - 24 - 24 - 24 4 2 2 - 24 4 2 2 - 24
-- --

100-pin TQFP 0x0E108069 68-pin QFN 48-SSOP 68-pin QFN 48-SSOP 48-SSOP 48-SSOP 0x0E120069 0x0E137069 0x0E11A069 0x0E10E069 0x0E110069 0x0E11B069
1x12-bit SAR
2422
-
1 x 12-bit SAR 2 1 x 12-bit SAR 2
- -

100-pin TQFP 0x0E16A069
1x12-bit SAR 1x12-bit SAR 1x12-bit SAR
2422 2422 2422
1 x 12-bit SAR 2 1 x 12-bit SAR 2
-

100-pin TQFP 0x0E158069 100-pin TQFP 0x0E123069
Document Number: 001-55035 Rev. *G
Page 92 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
12.1 Part Numbering Conventions
PSoC 5 devices follow the part numbering convention described here. All fields are single character alphanumeric (0, 1, 2, ..., 9, A, B, ..., Z) unless stated otherwise. CY8Cabcdefg-xxx
a: Architecture ef: Package code
3: PSoC 3 5: PSoC 5
b: Family group within architecture
2: CY8C52 family 3: CY8C53 family 4: CY8C54 family 5: CY8C55 family

Two character alphanumeric AX: TQFP LT: QFN PV: SSOP

g: Temperature range
c: Speed grade

C: commercial I: industrial A: automotive

4: 40 MHz 8: 80 MHz
xxx: Peripheral set

d: Flash capacity
Three character numeric No meaning is associated with these three characters
5: 32 KB 6: 64 KB 7: 128 KB 8: 256 KB

Examples
Cypress Prefix 5: PSoC 5 3: CY8C53 Family 8: 80 MHz 8: 256 KB AX: TQFP, PV: SSOP I: Industrial Architecture Family Group within Architecture Speed Grade Flash Capacity Package Code Temperature Range Peripheral Set
CY8C
5 3 8 8 AX /PV I
-xxx
All devices in the PSoC 5 CY8C53 family comply to RoHS-6 specifications, demonstrating the commitment by Cypress to lead-free products. Lead (Pb) is an alloying element in solders that has resulted in environmental concerns due to potential toxicity. Cypress uses nickel-palladium-gold (NiPdAu) technology for the majority of leadframe-based packages. A high level review of the Cypress Pb-free position is available on our website. Specific package information is also available. Package Material Declaration Datasheets (PMDDs) identify all substances contained within Cypress packages. PMDDs also confirm the absence of many banned substances. The information in the PMDDs will help Cypress customers plan for recycling or other "end of life" requirements.
Document Number: 001-55035 Rev. *G
Page 93 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
13. Packaging
Table 13-1. Package Characteristics Parameter TA TJ TJA TJA Tjc TJC TJC Description Operating ambient temperature Operating junction temperature Package JA (68 QFN) Package JA (100 TQFP) Package JC (48 SSOP) Package JC (68 QFN) Package JC (100 TQFP) Pb-free assemblies (20s to 40s) - Sn-Ag-Cu solder paste reflow temperature Pb-free assemblies (20s to 40s) - Sn-Pb solder paste reflow temperature Table 13-2. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Package 48-pin SSOP 68-pin QFN 100-pin TQFP MSL MSL 1 MSL 3 MSL 3 Figure 13-1. 48-pin (300 mil) SSOP Package Outline
.020
24 1
Conditions
Min -40 -40 - - - - 235
Typ 25 - 10.93 29.50 25.48 6.08 7.32 -
Max 85 100 - - - - 245
Units C C C/Watt C/Watt C/Watt C/Watt C/Watt C
205
-
220
C
0.395 0.420 0.292 0.299
DIMENSIONS IN INCHES MIN.
MAX.
25
48
0.620 0.630
0.088 0.092
0.095 0.110
SEATING PLANE GAUGE PLANE
.010
0.005 0.010
0.025 BSC
0.004
0.008 0.0135 0.008 0.016 0-8
0.024 0.040
51-85061-*D
Document Number: 001-55035 Rev. *G
Page 94 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Figure 13-2. 68-pin QFN 8x8 with 0.4 mm Pitch Package Outline (Sawn Version)
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.9000.100 8.0000.100 0.200 REF 5.70.10 0.400 PITCH PIN1 ID R 0.20
6 8 1
PIN 1 DOT
5 2 5 1 5 1
5 2
6 8
1
8.0000.100
5.70.10
0.200.05
1 7 1 8 3 4
3 5
0.05 MAX
SEATING PLANE
0.4000.1005
3 3 4
6.40 REF
1 8
1 7
NOTES: 1. HATCH AREA IS SOLDERABLE EXPOSED METAL.
0.08
C
001-09618 *C
2. REFERENCE JEDEC#: MO-220 3. PACKAGE WEIGHT: 0.17g 4. ALL DIMENSIONS ARE IN MILLIMETERS
Figure 13-3. 100-pin TQFP (14 x 14 x 1.4 mm) Package Outline
16.000.25 SQ 14.000.05 SQ 100 76
NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
1
75
3. DIMENSIONS IN MILLIMETERS
0.220.05
0 MIN. STAND-OFF 0.05 MIN. 0.15 MAX.
R 0.08 MIN. 0.20 MAX.
0.25 GAUGE PLANE
0.50 TYP. 25 51
R 0.08 MIN. 0.20 MAX. DETAIL
0-7 0 0 12.0000 0.600.15
A
26
50
NOTE: PKG. CAN HAVE
SEATING PLANE 1.60 MAX.
121 (8X) TOP LEFT CORNER CHAMFER
OR
1.400.05 0.08 0.20 MAX. SEE DETAIL
4 CORNERS CHAMFER
A
51-85048-*D
Document Number: 001-55035 Rev. *G
Page 95 of 102
6.40 REF
LASER MARK
SOLDERABLE EXPOSED PAD
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
14. Acronyms
Table 14-1. Acronyms Used in this Document Acronym abus ADC AG AHB analog local bus analog-to-digital converter analog global AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus arithmetic logic unit analog multiplexer bus application programming interface application program status register advanced RISC machine, a CPU architecture automatic thump mode bandwidth Controller Area Network, a communications protocol common-mode rejection ratio central processing unit cyclic redundancy check, an error-checking protocol digital-to-analog converter, see also IDAC, VDAC digital filter block digital input/output, GPIO with only digital capabilities, no analog. See GPIO. direct memory access, see also TD differential nonlinearity, see also INL port write data registers digital logic reset digital system interconnect data watchpoint and trace error correcting code external crystal oscillator electrically erasable programmable read-only memory electromagnetic interference external memory interface end of conversion end of frame execution program status register electrostatic discharge embedded trace macrocell Description
Table 14-1. Acronyms Used in this Document (continued) Acronym FIR FPB FS GPIO HVI IC IDAC IDE I2C, IIR ILO IMO INL I/O IPOR IPSR IRQ ITM LCD LIN LR LUT LVD LVI LVTTL MAC MCU MISO NC NMI NRZ NVIC NVL opamp PAL PC PCB PGA or IIC Description finite impulse response, see also IIR flash patch and breakpoint full-speed general-purpose input/output, applies to a PSoC pin high-voltage interrupt, see also LVI, LVD integrated circuit current DAC, see also DAC, VDAC integrated development environment Inter-Integrated Circuit, a communications protocol infinite impulse response, see also FIR internal low-speed oscillator, see also IMO internal main oscillator, see also ILO integral nonlinearity, see also DNL input/output, see also GPIO, DIO, SIO, USBIO initial power-on reset interrupt program status register interrupt request instrumentation trace macrocell liquid crystal display Local Interconnect Network, a communications protocol. link register lookup table low-voltage detect, see also LVI low-voltage interrupt, see also HVI low-voltage transistor-transistor logic multiply-accumulate microcontroller unit master-in slave-out no connect nonmaskable interrupt non-return-to-zero nested vectored interrupt controller nonvolatile latch, see also WOL operational amplifier programmable array logic, see also PLD program counter printed circuit board programmable gain amplifier
Page 96 of 102
ALU AMUXBUS API APSR ARM(R) ATM BW CAN CMRR CPU CRC DAC DFB DIO DMA DNL DR DRES DSI DWT ECC ECO EEPROM EMI EMIF EOC EOF EPSR ESD ETM
Document Number: 001-55035 Rev. *G
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Table 14-1. Acronyms Used in this Document (continued) Acronym PHUB PHY PICU PLA PLD PLL PMDD POR PRES PRS PS PSoC(R) PSRR PWM RAM RISC RMS RTC RTL RTR RX SAR SC/CT SCL SDA S/H SIO SNR SOC peripheral hub physical layer port interrupt control unit programmable logic array programmable logic device, see also PAL phase-locked loop package material declaration datasheet power-on reset precise power-on reset pseudo random sequence port read data register Programmable System-on-ChipTM power supply rejection ratio pulse-width modulator random-access memory reduced-instruction-set computing root-mean-square real-time clock register transfer language remote transmission request receive successive approximation register switched capacitor/continuous time I2C serial clock I2C serial data sample and hold special input/output, GPIO with advanced features. See GPIO. signal-to-noise ratio start of conversion Description
Table 14-1. Acronyms Used in this Document (continued) Acronym SOF SPI SR SRAM SRES SWD SWV TD THD TIA TRM TTL TX UART UDB USB USBIO VDAC WDT WOL WRES XRES XTAL start of frame Serial Peripheral Interface, a communications protocol slew rate static random access memory software reset serial wire debug, a test protocol single-wire viewer transaction descriptor, see also DMA total harmonic distortion transimpedance amplifier technical reference manual transistor-transistor logic transmit Universal Asynchronous Transmitter Receiver, a communications protocol universal digital block Universal Serial Bus USB input/output, PSoC pins used to connect to a USB port voltage DAC, see also DAC, IDAC watchdog timer write once latch, see also NVL watchdog timer reset external reset I/O pin crystal Description
15. Reference Documents
PSoC(R) 3, PSoC(R) 5 Architecture TRM PSoC(R) 5 Registers TRM
Document Number: 001-55035 Rev. *G
Page 97 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
16. Document Conventions
16.1 Units of Measure
Table 16-1. Units of Measure Symbol C dB fF Hz KB kbps Khr kHz k ksps LSB Mbps MHz M Msps A F H s V W mA ms mV nA ns nV pF ppm ps s sps sqrtHz V decibels femtofarads hertz 1024 bytes kilobits per second kilohours kilohertz kilohms kilosamples per second least significant bit megabits per second megahertz megaohms megasamples per second microamperes microfarads microhenrys microseconds microvolts microwatts milliamperes milliseconds millivolts nanoamperes nanoseconds nanovolts ohms picofarads parts per million picoseconds seconds samples per second square root of hertz volts Unit of Measure degrees Celsius
Document Number: 001-55035 Rev. *G
Page 98 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
17. Revision History
Description Title: PSoC(R) 5: CY8C53 Family Datasheet Programmable System-on-Chip (PSoC(R)) Document Number: 001-55035 Rev. ** *A ECN No. 2759055 2824626 Submission Date 09/02/09 12/09/09 Orig. of Change MKEA MKEA Description of Change New datasheet for new device CY8C53 Family Datasheet. Updated I2C section to reflect 1 Mbps. Updated Table 11-6 and 11- 7 (Boost AC and DC specs); also added Shottky Diode specs. Changed current for sleep/hibernate mode to include SIO; Added footnote to analog global specs. Updated Figures 1-1, 6-2, 7-14, and 8-1. Updated Table 6-2 and Table 6-3 (Hibernate and Sleep rows) and Power Modes section. Updated GPIO and SIO AC specifications. Updated Gain error in IDAC and VDAC specifications. Updated description of VDDA spec in Table 11-1 and removed GPIO Clamp Current parameter. Moved FILO from ILO DC to AC table. Added PCB Layout and PCB Schematic diagrams. Updated Fgpioout spec (Table 11-9). Added duty cycle frequency in PLL AC spec table. Added note for Sleep and Hibernate modes and Active Mode specs in Table 11-2. Linked URL in Section 10.3 to PSoC Creator site. Updated Ja and Jc values in Table 13-1. Updated Single Sample Mode and Fast FIR Mode sections. Updated Input Resistance specification in Del-Sig ADC table. Added Tio_init parameter. Updated PGA and UGB AC Specs. Removed SPC ADC. Updated Boost Converter section. Added section 'SIO as Comparator'; updated Hysteresis spec (differential mode) in Table 11-10. Updated VBAT condition and deleted Vstart parameter in Table 11-6. Removed reference to Idle mode. CDT 59671: Updated footnotes and ADC column in ordering information. Removed CSA (Section 8.7). Updated IMO table and number of UDBs Changed maximum value of PPOR_TR to '1'. Updated VBIAS specification. Updated Figure 8-1 and Figure 6-3. Updated Interrupt Vector table, Updated Sales links. Updated JTAG and SWD specifications. Removed Jp-p and Jperiod from ECO AC Spec table. Added note on sleep timer in Table 11-2. Updated ILO AC and DC specifications. Added Resolution parameter in VDAC and IDAC tables. Updated IOUT typical and maximum values. Changed Temperature Sensor range to -40 C to +85 C. Removed Latchup specification from Table 11-1
*B
2873520
02/04/10
MKEA
Document Number: 001-55035 Rev. *G
Page 99 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Description Title: PSoC(R) 5: CY8C53 Family Datasheet Programmable System-on-Chip (PSoC(R)) Document Number: 001-55035 *C 2911720 04/13/10 MKEA Updated Vb pin in PCB Schematic. Updated Tstartup parameter in AC Specifications table. Added Load regulation and Line regulation parameters to Inductive Boost Regulator DC Specifications table. Updated ICC parameter in LCD Direct Drive DC Specs table. In page 1, updated internal oscillator range under Precision programmable clocking to start from 3 MHz. Updated IOUT parameter in LCD Direct Drive DC Specs table. Updated Table 6-2 and Table 6-3. Added bullets on CapSense in page 1; added CapSense column in Section 12. Removed some references to footnote [1]. Added footnote in PLL AC Specification table. Added PLL intermediate frequency row with footnote in PLL AC Specs table. Added UDBs subsection under 11.6 Digital Peripherals. Updated Figure 2-6 (PCB Layout). Updated Pin Descriptions section and modified Figures 6-6, 6-8, 6-9. Updated LVD in Tables 6-2 and 6-3; modified Low power modes bullet in page 1. Added note to Figures 2-5 and 6-2; Updated Figure 6-2 to add capacitors for VDDA and VDDD pins. Updated boost converter section (6.2.2). Updated Tstartup values in Table 11-3. Removed IPOR rows from Table 11-68. Updated 6.3.1.1, Power Voltage Level Monitors. Updated section 5.2 and Table 11-2 to correct suggestion of execution from flash. Updated VREF specs in Table 11-21. Updated IDAC uncompensated gain error in Table 11-25. Added sentence to last paragraph of section 6.1.1.3. Updated TRESP, high and low power modes, in Table 11-24. Updated f_TCK values in Table 11-73 and f_SWDCK values in Table 11-74. Updated SNR condition in Table 11-20. Corrected unit of measurement in Table 11-21. Updated sleep wakeup time in Table 6-3 and Tsleep in Table 11-3. Added 1.71 V <= VDDD < 3.3 V, SWD over USBIO pins value to Table 11-74. Removed mention of hibernate reset (HRES) from page 1 features, Table 6-3, Section 6.2.1.4, Section 6.3, and Section 6.3.1.1. Changed PPOR/PRES to TBDs in Section 6.3.1.1, Section 6.4.1.6 (changed PPOR to reset), Table 11-3 (changed PPOR to PRES), Table 11-68 (changed title, values TBD), and Table 11-69 (changed PPOR_TR to PRES_TR). Added sentence saying that LVD circuits can generate a reset to Section 6.3.1.1. Changed IDD values on page 1, page 5, and Table 11-2. Changed resume time value in Section 6.2.1.3. Changed ESD HBM value in Table 11-1. Removed VDDA = 1.65 V rows and changed BWag value in Table 11-22. Changed VIOFF values and changed CMRR value in Table 11-23. Changed INL max value in Table 11-27. Added max value to the Quiescent current specs in Tables 11-29 and 11-31. Changed occurrences of "Block" to "Row" and deleted the "ECC not included" footnote in Table 11-57. Changed max response time value in Tables 11-69 and 11-71. Changed the Startup time in Table 11-79. Added condition to intermediate frequency row in Table 11-85. Added row to Table 11-69. Added brown out note to Section 11.8.1.
Document Number: 001-55035 Rev. *G
Page 100 of 102
[+] Feedback
PRELIMINARY
PSoC(R) 5: CY8C53 Family Datasheet
Description Title: PSoC(R) 5: CY8C53 Family Datasheet Programmable System-on-Chip (PSoC(R)) Document Number: 001-55035 *D 2936486 05/24/10 MKEA Replaced VDDIO with VDDD in USBIO diagram and specification tables, added text in USBIO section of Electrical Specifications. Added Table 13-2 (Package MSL) Modified Tstorag condition and changed maximum value to 100 Added bullet (Pass) in ALU (section 7.2.2.2) Added figures for kHzECO and MHzECO in the External Oscillator section Updated Figure 6-1(Clocking Subsystem diagram) Resolved discrepancies with the EROS in Electrical Specifications sections Updated PSoC Creator Framework image Updated SIO DC Specifications (VIH and VIL parameters) Updated values in Low power modes bullet on page 1 Updated Figure 8-2 Updated PCB Layout and Schematic, updates as per MTRB review comments Updated Table 6-3 (power changed to current) In 32kHZ EC DC Specifications table , changed ICC Max to 0.25 In IMO DC Specifications table, updated Supply Current values Updated GPIO DC Specs table Removed all references to 48-SSOP package Minor update to post to cypress.com. Corrected typo in Table 11-3 (V/ms to V/ns) and Tables 11-29 and 11-31 (A to mA) Added USBIO 22 ohm DP and DM resistors to Simplified Block Diagram Added to Table 6-6 a footnote and references to same. Added sentences to the resistive pull-up and pull-down description bullets. Added sentence to Section 6.4.11, Adjustable Output Level. Updated section 5.5 External Memory Interface Updated Table 11-73 JTAG Interface AC Specifications Updated Table 11-74 SWD Interface AC Specifications A footnote, TRACEPORT / TRACECLK max frequency is limited by GPIO max frequency, is added to the section 11.8.6. 48-SSOP package added.
*E *F *G
2944841 2960407 3019464
6/4/2010 06/24/10 08/31/10
FSU MKEA MKEA
Document Number: 001-55035 Rev. *G
Page 101 of 102
[+] Feedback
PRELIMINARY PSoC(R) 5: CY8C53 Family Datasheet
18. Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturers' representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.
Products
Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless
PSoC Solutions
psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5
(c) Cypress Semiconductor Corporation, 2009-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-55035 Rev. *G
(R) (R) (R) (R) (R)
Revised September 2, 2010
Page 102 of 102
CapSense , PSoC 3, PSoC 5, and PSoC CreatorTM are trademarks and PSoC is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ARM is a registered trademark, and Keil, and RealView are trademarks, of ARM Limited. All products and company names mentioned in this document may be the trademarks of their respective holders.
[+] Feedback

▲Up To Search▲

Price & Availability of CY8C5387PVI-031

	To Download CY8C5387PVI-031 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .